ARM: dts: stm32mp1: Add usb gadget support for stm32mp157c-ev1 board

Add DT nodes to enable DWC2 gadget support

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi
index c69c397964afe51b4bf5ae1bdb8612a36a5c9311..85da5926551c608124ae54288c5762d147517aae 100644 (file)
--- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi
@@ -321,6 +321,12 @@
                                        bias-disable;
                                };
                        };
+
+                       usbotg_hs_pins_a: usbotg_hs-0 {
+                               pins {
+                                       pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
+                               };
+                       };
                };
 
                pinctrl_z: pin-controller-z@54004000 {

diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
index 2f4de3a066c0c0f48e758ffe7365f607225f5c2f..30b173478c6ca8a1243090b23f891b6edefd8e37 100644 (file)
--- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
@@ -25,6 +25,10 @@
        regulator-always-on;
 };
 
+&usbotg_hs {
+       g-tx-fifo-size = <576>;
+};
+
 /* SPL part **************************************/
 &qspi {
        u-boot,dm-spl;
@@ -60,3 +64,4 @@
 &flash0 {
        u-boot,dm-spl;
 };
+

diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index d6934f74e076c6b7c5abb6fb29d0fe4baa2dcbea..e2128af93fe566a3c98c876d341173b006371c82 100644 (file)
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -96,6 +96,14 @@
        };
 };
 
+&usbotg_hs {
+       pinctrl-names = "default";
+       pinctrl-0 = <&usbotg_hs_pins_a>;
+       phys = <&usbphyc_port1 0>;
+       phy-names = "usb2-phy";
+       status = "okay";
+};
+
 &usbphyc {
        status = "okay";
 };

diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index cdf2946968828bf5d827ddbfda76c747a2770652..33c5981869b30281a025c2112d77365af2965843 100644 (file)
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -106,6 +106,26 @@
                };
        };
 
+       pm_domain {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "st,stm32mp157c-pd";
+
+               pd_core_ret: core-ret-power-domain@1 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <1>;
+                       #power-domain-cells = <0>;
+                       label = "CORE-RETENTION";
+
+                       pd_core: core-power-domain@2 {
+                               reg = <2>;
+                               #power-domain-cells = <0>;
+                               label = "CORE";
+                       };
+               };
+       };
+
        soc {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -654,6 +674,22 @@
                        status = "disabled";
                };
 
+               usbotg_hs: usb-otg@49000000 {
+                       compatible = "st,stm32mp1-hsotg", "snps,dwc2";
+                       reg = <0x49000000 0x10000>;
+                       clocks = <&rcc USBO_K>;
+                       clock-names = "otg";
+                       resets = <&rcc USBO_R>;
+                       reset-names = "dwc2";
+                       interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+                       g-rx-fifo-size = <256>;
+                       g-np-tx-fifo-size = <32>;
+                       g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
+                       dr_mode = "otg";
+                       power-domains = <&pd_core>;
+                       status = "disabled";
+               };
+
                rcc: rcc@50000000 {
                        compatible = "st,stm32mp1-rcc", "syscon";
                        reg = <0x50000000 0x1000>;