pci: Fix configuring io/memory base and limit registers of PCI bridges

Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved
and should be zero. So do not set them to non-zero value.

Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers
contain information if 64-bit memory addressing is supported. So preserve
this information when overwriting these registers.

Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information
if 32-bit io addressing is supported. So preserve this information and do
not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and
PCI_IO_LIMIT_UPPER16 registers) when it is unsupported.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index b128a05dd38042ea554c92bc8237fcf03fd0ffd5..7b6e629cae702e85b6ff55623db0fc5519160c3f 100644 (file)
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -165,6 +165,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
        struct pci_region *pci_prefetch;
        struct pci_region *pci_io;
        u16 cmdstat, prefechable_64;
+       u8 io_32;
        struct udevice *ctlr = pci_get_controller(dev);
        struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
 
@@ -175,6 +176,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
        dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
        dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
        prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
+       dm_pci_read_config8(dev, PCI_IO_LIMIT, &io_32);
+       io_32 &= PCI_IO_RANGE_TYPE_MASK;
 
        /* Configure bus number registers */
        dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
@@ -191,7 +194,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
                 * I/O space
                 */
                dm_pci_write_config16(dev, PCI_MEMORY_BASE,
-                                     (pci_mem->bus_lower & 0xfff00000) >> 16);
+                                     ((pci_mem->bus_lower & 0xfff00000) >> 16) &
+                                     PCI_MEMORY_RANGE_MASK);
 
                cmdstat |= PCI_COMMAND_MEMORY;
        }
@@ -205,7 +209,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
                 * I/O space
                 */
                dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
-                               (pci_prefetch->bus_lower & 0xfff00000) >> 16);
+                               (((pci_prefetch->bus_lower & 0xfff00000) >> 16) &
+                               PCI_PREF_RANGE_MASK) | prefechable_64);
                if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 #ifdef CONFIG_SYS_PCI_64BIT
                        dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
@@ -217,8 +222,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
                cmdstat |= PCI_COMMAND_MEMORY;
        } else {
                /* We don't support prefetchable memory for now, so disable */
-               dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
-               dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
+               dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000 |
+                                                               prefechable_64);
+               dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 |
+                                                               prefechable_64);
                if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
                        dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
                        dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
@@ -230,8 +237,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
                pciauto_region_align(pci_io, 0x1000);
 
                dm_pci_write_config8(dev, PCI_IO_BASE,
-                                    (pci_io->bus_lower & 0x0000f000) >> 8);
-               dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
+                                    (((pci_io->bus_lower & 0x0000f000) >> 8) &
+                                    PCI_IO_RANGE_MASK) | io_32);
+               if (io_32 == PCI_IO_RANGE_TYPE_32)
+                       dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
                                      (pci_io->bus_lower & 0xffff0000) >> 16);
 
                cmdstat |= PCI_COMMAND_IO;
@@ -261,7 +270,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
                pciauto_region_align(pci_mem, 0x100000);
 
                dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
-                                     (pci_mem->bus_lower - 1) >> 16);
+                                     ((pci_mem->bus_lower - 1) >> 16) &
+                                     PCI_MEMORY_RANGE_MASK);
        }
 
        if (pci_prefetch) {
@@ -275,7 +285,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
                pciauto_region_align(pci_prefetch, 0x100000);
 
                dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
-                                     (pci_prefetch->bus_lower - 1) >> 16);
+                                     (((pci_prefetch->bus_lower - 1) >> 16) &
+                                      PCI_PREF_RANGE_MASK) | prefechable_64);
                if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 #ifdef CONFIG_SYS_PCI_64BIT
                        dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
@@ -286,12 +297,20 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
        }
 
        if (pci_io) {
+               u8 io_32;
+
+               dm_pci_read_config8(dev, PCI_IO_LIMIT,
+                                    &io_32);
+               io_32 &= PCI_IO_RANGE_TYPE_MASK;
+
                /* Round I/O allocator to 4KB boundary */
                pciauto_region_align(pci_io, 0x1000);
 
                dm_pci_write_config8(dev, PCI_IO_LIMIT,
-                               ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
-               dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
+                               ((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) &
+                               PCI_IO_RANGE_MASK) | io_32);
+               if (io_32 == PCI_IO_RANGE_TYPE_32)
+                       dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
                                ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
        }
 }