board: ge: bx50v3: Enable CONFIG_DM_SPI, CONFIG_DM_SPI_FLASH

Use SPI flash device model, and remove SPI pin configuration code since
the pinctrl driver is used.

Signed-off-by: Ian Ray <ian.ray@ge.com>

diff --git a/arch/arm/dts/imx6q-bx50v3.dts b/arch/arm/dts/imx6q-bx50v3.dts
index 0fff2195f985985a28314c42fce63414d026ef6c..deaec635093778f4d0aeeb584c7d7dd726d9461e 100644 (file)
--- a/arch/arm/dts/imx6q-bx50v3.dts
+++ b/arch/arm/dts/imx6q-bx50v3.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 #include "imx6q.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
        model = "General Electric Bx50v3";
@@ -17,6 +18,16 @@
 &iomuxc {
        pinctrl-names = "default";
 
+       pinctrl_ecspi1: ecspi1grp {
+               fsl,pins = <
+                       MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+                       MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+                       MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+                       /* SPI1 CS */
+                       MX6QDL_PAD_EIM_EB2__GPIO2_IO30  0x1b0b0
+               >;
+       };
+
        pinctrl_usdhc3: usdhc3grp {
                fsl,pins = <
                        MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
@@ -60,3 +71,19 @@
 &usdhc4 {
        status = "disabled";
 };
+
+/* SPI NOR */
+&ecspi1 {
+       cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi1>;
+       status = "okay";
+
+       flash: n25q032@0 {
+               compatible = "jedec,spi-nor";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               spi-max-frequency = <20000000>;
+               reg = <0>;
+       };
+};

diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index dac063dc430a82611346aa9ffae7b40ef072fce9..b69b9e727ba1d4ddcbcfd3c5cdcac43b846e5d0e 100644 (file)
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -53,9 +53,6 @@ static struct vpd_cache vpd;
 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
        PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
 
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
-                     PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
        PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
        PAD_CTL_ODE | PAD_CTL_SRE_FAST)
@@ -113,13 +110,6 @@ static void setup_iomux_enet(void)
        mdelay(1);
 }
 
-static iomux_v3_cfg_t const ecspi1_pads[] = {
-       MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-       MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
-       MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
-       MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
 static struct i2c_pads_info i2c_pad_info1 = {
        .scl = {
                .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
@@ -159,18 +149,6 @@ static struct i2c_pads_info i2c_pad_info3 = {
        }
 };
 
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
-       return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
-}
-
-static void setup_spi(void)
-{
-       imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-}
-#endif
-
 static iomux_v3_cfg_t const pcie_pads[] = {
        MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
        MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -594,9 +572,6 @@ int board_init(void)
        /* address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-#ifdef CONFIG_MXC_SPI
-       setup_spi();
-#endif
        return 0;
 }
 

diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index 1acda9ec74c4be2708c204807c7cd00132f88608..14114acbcefaaad9a0edf02c4dcedf25101eae71 100644 (file)
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -59,3 +59,5 @@ CONFIG_BLK=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y