powerpc/85xx: Fix NAND SPL support

We cause CCSRBAR to be relocated in the SPL phase of NAND boot which
isn't expected and breaks things.  Fixing the board config.h to NOT
relocate CCSR during the CONFIG_NAND_SPL phase.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index d4e3ef5c2c0e2399782531688664eaa0b89fc927..16db98fe57cc09ade05355328ed085d32922d0f6 100644 (file)
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -131,7 +131,7 @@
 #define CONFIG_SYS_CCSRBAR             0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
 
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 

diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 19d32718fab2d64761f64418288e5aee6b7d32c5..ab27b9895a2b4aaed05c7acd4681de4c63ffe5d9 100644 (file)
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -108,7 +108,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_CCSRBAR             0xe0000000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
 
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 

diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index ffee8fc8b0163e23f1081e5fb286d143f3897b0f..d7910e1c731f4e5bd30de4947fbe04bb3b63cd84 100644 (file)
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -115,7 +115,7 @@
 #define CONFIG_SYS_CCSRBAR             0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
 
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 

diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 883d44e37105d2eabd596a8bb7ed821c63895134..00fa74d6f7b6261ae6548fe411474d9ffb8ca0da 100644 (file)
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -151,7 +151,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_CCSRBAR             0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
 
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index bcfb0348404d33c83782c8d10b6e9cdb39528312..5a69902f899b96e2bb31416d08d18366a0eb80eb 100644 (file)
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -221,7 +221,7 @@
 
 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
        SPL code*/
-#if defined(CONFIG_NAND_U_BOOT) && defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif