#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <500000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <750000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0xe0000000 0x10000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
clocks {
compatible = "simple-bus";
- u-boot,dm-pre-reloc;
+ bootph-all;
apbclk: apbclk {
compatible = "fixed-clock";
compatible = "fixed-clock";
clock-frequency = <33333333>;
#clock-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
mmcclk_ciu: mmcclk-ciu {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <40000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <500000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <144000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <70000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
timer@0 {
compatible = "snps,arc-timer";
/ {
ocp {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&l4_wkup {
- u-boot,dm-pre-reloc;
+ bootph-all;
segment@200000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
target-module@0
{
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
};
target-module@7000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
};
target-module@9000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
};
};
};
&wkup_cm {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&l4_wkup_clkctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&l4_per {
- u-boot,dm-pre-reloc;
+ bootph-all;
segment@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
target-module@4c000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
};
};
segment@100000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
target-module@ac000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
};
target-module@ae000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
};
};
};
&prcm {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio0_target {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&prcm_clocks {
};
&i2c0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&uart0 { /* console uart */
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
};
};
&i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
clock-frequency = <100000>;
tps: tps@24 { /* PMIC controller */
- u-boot,dm-spl;
+ bootph-pre-ram;
reg = <0x24>;
compatible = "ti,tps65217";
};
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
};
&spi0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
cs-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>,
spi-max-frequency = <24000000>;
spi_flash: spiflash@0 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
compatible = "spidev", "spi-flash";
spi-max-frequency = <24000000>;
reg = <0>;
};
&spi1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
cs-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>,
<&gpio0 19 GPIO_ACTIVE_HIGH>,
segment@300000 {
target-module@e000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
lcdc: lcdc@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,no-reset-on-init;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,no-reset-on-init;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,no-reset-on-init;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,no-reset-on-init;
};
};
&uart0 { /* console uart */
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
};
};
&i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
clock-frequency = <100000>;
tps: tps@24 { /* PMIC controller */
- u-boot,dm-spl;
+ bootph-pre-ram;
reg = <0x24>;
compatible = "ti,tps65217";
};
&mmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x4>;
ti,non-removable;
};
&mmc2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x8>;
ti,non-removable;
segment@300000 {
target-module@e000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
lcdc: lcdc@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,no-reset-on-init;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,no-reset-on-init;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,no-reset-on-init;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,no-reset-on-init;
};
#include "am33xx-u-boot.dtsi"
&l4_per {
- u-boot,dm-pre-reloc;
+ bootph-all;
segment@300000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
target-module@e000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
lcdc: lcdc@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
};
&i2c0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&l4_wkup {
- u-boot,dm-pre-reloc;
+ bootph-all;
segment@200000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
target-module@9000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
segment@300000 {
target-module@e000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
lcdc: lcdc@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
/ {
ocp {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&l4_wkup {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&l4_per {
segment@300000 {
target-module@e000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
lcdc: lcdc@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
};
&mmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc1_pins {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&scm {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&spi0 {
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0_pins {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usb {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usb_ctrl_mod {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usb0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usb0_phy {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&am33xx_pinmux {
- u-boot,dm-pre-reloc;
+ bootph-all;
lcd0_pins: pinmux_lcd0_pins {
pinctrl-single,pins = <
#include "am33xx-u-boot.dtsi"
&l4_wkup {
- u-boot,dm-pre-reloc;
+ bootph-all;
segment@200000 {
target-module@10000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&l4_per {
- u-boot,dm-pre-reloc;
+ bootph-all;
segment@100000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
target-module@a6000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
segment@300000 {
target-module@e000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
lcdc: lcdc@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
};
&scm {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&am33xx_pinmux {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart3_pins {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc1_pins {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc2_pins {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
segment@300000 {
target-module@e000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
lcdc: lcdc@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
};
ocp {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&i2c0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
segment@300000 {
target-module@e000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
lcdc: lcdc@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&l4_wkup {
segment@200000 {
target-module@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&prcm {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&per_cm {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&l4ls_clkctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&l4_per {
- u-boot,dm-pre-reloc;
+ bootph-all;
segment@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
target-module@30000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&spi0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
channel@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
/ {
ocp {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&l4_wkup {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&scm {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&am33xx_pinmux {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0_pins {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
&emmc_pins {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc1_pins {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc3 {
};
ocp {
- u-boot,dm-pre-reloc;
+ bootph-all;
l4_wkup@44c00000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
segment@200000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
target-module@9000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
};
&i2c0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
};
/ {
ocp {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&gpio1 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio2 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio3 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio5 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio6 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&mmc2 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&mmc3 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&uart1 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&uart2 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
/{
ocp {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&i2c0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&dwc3_1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb2_phy1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&am43xx_control_usb2phy1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ocp2scp0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dwc3_2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb2_phy2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&am43xx_control_usb2phy2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ocp2scp1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/{
ocp {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mac {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&davinci_mdio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cpsw_emac0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&phy_sel {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&l4_wkup {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&scm {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&scm_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
ðphy0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/{
ocp {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
xtal25mhz: xtal25mhz {
};
&uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
cdce913: cdce913@65 {
compatible = "ti,cdce913";
};
&mmc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/{
ocp {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&spi0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
spi-flash@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ð0 {
};
&spi0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
spi-flash@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_sb {
// SPDX-License-Identifier: GPL-2.0
&watchdog {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#include "mvebu-u-boot.dtsi"
};
&i2c0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
i2cmux: i2cmux@70 {
- u-boot,dm-pre-reloc;
+ bootph-all;
i2c@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
i2c@1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
i2c@5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
crypto@64 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
// SPDX-License-Identifier: GPL-2.0+
&spi1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
spi-flash@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdhci {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ahci0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ahci1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
eeprom@52 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
eeprom@53 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&spi1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
spi-flash@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&w25q32 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ahci0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ahci1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdhci {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
eeprom@52 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
eeprom@53 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&gpio0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&spi1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&I2C0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&PCA22 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#include "mvebu-u-boot.dtsi"
cpu@000 {
clocks;
- u-boot,dm-pre-reloc;
+ bootph-all;
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x000>;
};
cpu@001 {
clocks;
- u-boot,dm-pre-reloc;
+ bootph-all;
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x001>;
};
cpu@100 {
clocks;
- u-boot,dm-pre-reloc;
+ bootph-all;
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x100>;
};
cpu@101 {
clocks;
- u-boot,dm-pre-reloc;
+ bootph-all;
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x101>;
&lcd0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#include "mvebu-u-boot.dtsi"
};
&uart5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&wdt1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&wdt2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&wdt3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
scu: clock-controller@1e6e2000 {
compatible = "aspeed,ast2500-scu";
reg = <0x1e6e2000 0x1000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <1>;
#reset-cells = <1>;
};
rst: reset-controller {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "aspeed,ast2500-reset";
#reset-cells = <1>;
};
sdrammc: sdrammc@1e6e0000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "aspeed,ast2500-sdrammc";
reg = <0x1e6e0000 0x174
0x1e6e0200 0x1d4 >;
};
&timer {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mac0 {
};
&uart5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&hace {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&acry {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
scu: clock-controller@1e6e2000 {
compatible = "aspeed,ast2600-scu";
reg = <0x1e6e2000 0x1000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <1>;
#reset-cells = <1>;
uart-clk-source = <0x0>; /* uart clock source selection: 0: uxclk 1: huxclk*/
};
rst: reset-controller {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "aspeed,ast2600-reset";
aspeed,wdt = <&wdt1>;
#reset-cells = <1>;
};
sdrammc: sdrammc@1e6e0000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "aspeed,ast2600-sdrammc";
reg = <0x1e6e0000 0x100
0x1e6e0100 0x300
};
ahb {
- u-boot,dm-pre-reloc;
+ bootph-all;
apb {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
/ {
ahb {
- u-boot,dm-pre-reloc;
+ bootph-all;
apb {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&clk32 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&dbgu {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&main_rc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&main_xtal {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_dbgu {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pioA {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pioB {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pit64b0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&slow_rc_osc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&slow_xtal {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &uart1;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_default>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
apb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
i2c0: i2c@f8028000 {
pit: timer@f8048030 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
sfr: sfr@f8030000 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioA: pinctrl@fc038000 {
<PIN_PA20__SDMMC1_DAT2>,
<PIN_PA21__SDMMC1_DAT3>;
bias-pull-up;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ck_cd {
pinmux = <PIN_PA22__SDMMC1_CK>,
<PIN_PA30__SDMMC1_CD>;
bias-disable;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
pinmux = <PIN_PD2__URXD1>,
<PIN_PD3__UTXD1>;
bias-disable;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pinctrl_i2c0_default: i2c0_default {
compatible = "atmel,sama5d27-som1-ek", "atmel,sama5d2", "atmel,sama5";
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &uart1;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
sdmmc1: sdio-host@b0000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_default>;
status = "okay"; /* conflict with qspi0 */
- u-boot,dm-pre-reloc;
+ bootph-all;
};
apb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
display-timings {
- u-boot,dm-pre-reloc;
+ bootph-all;
480x272 {
clock-frequency = <9000000>;
hactive = <480>;
vfront-porch = <2>;
vback-porch = <2>;
vsync-len = <11>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioA: pinctrl@fc038000 {
<PIN_PA8__SDMMC0_DAT6>,
<PIN_PA9__SDMMC0_DAT7>;
bias-pull-up;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ck_cd {
<PIN_PA10__SDMMC0_RSTN>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
<PIN_PA20__SDMMC1_DAT2>,
<PIN_PA21__SDMMC1_DAT3>;
bias-pull-up;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ck_cd {
pinmux = <PIN_PA22__SDMMC1_CK>,
<PIN_PA30__SDMMC1_CD>;
bias-disable;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
pinmux = <PIN_PD2__URXD1>,
<PIN_PD3__UTXD1>;
bias-disable;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pinctrl_usb_default: usb_default {
/ {
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&hlcdc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi1_flash {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sfr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_sdmmc0_default {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_uart0_default {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_qspi1_default {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&pinctrl_mikrobus1_uart {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_qspi1_sck_cs_default {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_qspi1_dat_default {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_sdmmc0_default {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
flash@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&sdmmc0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 { /* mikrobus1 uart */
- u-boot,dm-pre-reloc;
+ bootph-all;
};
compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5";
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &uart0;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
sdmmc1: sdio-host@b0000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_default>;
status = "disabled"; /* conflicts with nand and qspi0*/
- u-boot,dm-pre-reloc;
+ bootph-all;
};
apb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
i2c1: i2c@fc028000 {
<PIN_PA8__SDMMC0_DAT6>,
<PIN_PA9__SDMMC0_DAT7>;
bias-pull-up;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ck_cd {
<PIN_PA11__SDMMC0_VDDSEL>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
<PIN_PA20__SDMMC1_DAT2>,
<PIN_PA21__SDMMC1_DAT3>;
bias-pull-up;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ck_cd {
pinmux = <PIN_PA22__SDMMC1_CK>,
<PIN_PA30__SDMMC1_CD>;
bias-disable;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pinctrl_usb_default: usb_default {
compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5";
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &uart1;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
sdmmc1: sdio-host@b0000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_default>;
status = "okay"; /* conflict with qspi0 */
- u-boot,dm-pre-reloc;
+ bootph-all;
};
apb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
display-timings {
- u-boot,dm-pre-reloc;
+ bootph-all;
480x272 {
clock-frequency = <9000000>;
hactive = <480>;
vfront-porch = <2>;
vback-porch = <2>;
vsync-len = <11>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi0_sck_cs_default &pinctrl_qspi0_dat_default>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <83000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
spi_flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
i2c1: i2c@fc028000 {
pinmux = <PIN_PA22__QSPI0_SCK>,
<PIN_PA23__QSPI0_CS>;
bias-disable;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pinctrl_qspi0_dat_default: qspi0_dat_default {
<PIN_PA26__QSPI0_IO2>,
<PIN_PA27__QSPI0_IO3>;
bias-pull-up;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pinctrl_sdmmc0_default: sdmmc0_default {
<PIN_PA8__SDMMC0_DAT6>,
<PIN_PA9__SDMMC0_DAT7>;
bias-pull-up;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ck_cd_default {
<PIN_PA11__SDMMC0_VDDSEL>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
<PIN_PA20__SDMMC1_DAT2>,
<PIN_PA21__SDMMC1_DAT3>;
bias-pull-up;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ck_cd {
pinmux = <PIN_PA22__SDMMC1_CK>,
<PIN_PA30__SDMMC1_CD>;
bias-disable;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
<PIN_PA15__SPI0_MOSI>,
<PIN_PA16__SPI0_MISO>;
bias-disable;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pinctrl_uart1_default: uart1_default {
pinmux = <PIN_PD2__URXD1>,
<PIN_PD3__UTXD1>;
bias-disable;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pinctrl_usb_default: usb_default {
compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5";
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &dbgu;
};
ahb {
apb {
mmc0: mmc@f0000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>;
vmmc-supply = <&vcc_mmc0_reg>;
vqmmc-supply = <&vcc_3v3_reg>;
};
mmc1: mmc@f8000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
vmmc-supply = <&vcc_3v3_reg>;
vqmmc-supply = <&vcc_3v3_reg>;
status = "disabled";
};
dbgu: serial@ffffee00 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
pinctrl@fffff200 {
board {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_i2c0_pu: i2c0_pu {
atmel,pins =
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
};
pinctrl_mmc0_cd: mmc0_cd {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_mmc1_cd: mmc1_cd {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
};
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &usart3;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb888>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
display-timings {
- u-boot,dm-pre-reloc;
+ bootph-all;
480x272 {
clock-frequency = <9000000>;
hactive = <480>;
vfront-porch = <2>;
vback-porch = <2>;
vsync-len = <11>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
spi0: spi@f8010000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
status = "okay";
spi_flash@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
mmc1: mmc@fc000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
vmmc-supply = <&vcc_mmc1_reg>;
};
usart3: serial@fc00c000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
pinctrl@fc06a000 {
board {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_mmc1_cd: mmc1_cd {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
};
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &usart3;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
display-timings {
- u-boot,dm-pre-reloc;
+ bootph-all;
800x480 {
clock-frequency = <33260000>;
hactive = <800>;
vfront-porch = <23>;
vback-porch = <22>;
vsync-len = <5>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
};
spi0: spi@f8010000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
status = "okay";
spi_flash@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
mmc1: mmc@fc000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
status = "okay";
};
usart3: serial@fc00c000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
pinctrl@fc06a000 {
board {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_macb0_phy_irq: macb0_phy_irq {
atmel,pins =
<AT91_PIOE 1 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
<AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_mmc1_cd: mmc1_cd {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
/ {
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
utmi {
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
usb2: usb@400000 {
compatible = "microchip,sama7g5-ohci", "usb-ohci";
};
&main_rc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&main_xtal {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pioA {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_flx3_default {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pioA {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_usb_default: usb_default {
pinmux = <PIN_PC6__GPIO>;
};
&pit64b0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&slow_rc_osc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&slow_xtal {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usb2 {
compatible = "atmel,at91sam9260", "atmel,at91sam9";
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &dbgu;
};
};
dbgu: serial@fffff200 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
aic: interrupt-controller@fffff000 {
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
atmel,clk-output-range = <0 105000000>;
atmel,clk-divisors = <1 2 4 0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
usb: usbck {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
- u-boot,dm-pre-reloc;
+ bootph-all;
pioA_clk: pioA_clk@2 {
#clock-cells = <0>;
reg = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioB_clk: pioB_clk@3 {
#clock-cells = <0>;
reg = <3>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioC_clk: pioC_clk@4 {
#clock-cells = <0>;
reg = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
adc_clk: adc_clk@5 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioB: gpio@fffff600 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioC: gpio@fffff800 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pinctrl: pinctrl@fffff400 {
0xffffffff 0x7fff3ccf /* pioB */
0xffffffff 0x007fffff /* pioC */
>;
- u-boot,dm-pre-reloc;
+ bootph-all;
/* shared pinctrl settings */
dbgu {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
compatible = "atmel,at91sam9260ek", "atmel,at91sam9260", "atmel,at91sam9";
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &dbgu;
};
};
dbgu: serial@fffff200 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
usb0: ohci@00500000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
tcb0: timer@fffa0000 {
compatible = "atmel,at91rm9200-tcb";
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioB: gpio@fffff600 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioC: gpio@fffff800 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pinctrl@fffff400 {
<0xffffffff 0xfffffff7>, /* pioA */
<0xffffffff 0xfffffff4>, /* pioB */
<0xffffffff 0xffffff07>; /* pioC */
- u-boot,dm-pre-reloc;
+ bootph-all;
/* shared pinctrl settings */
dbgu {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
atmel,clk-output-range = <0 94000000>;
atmel,clk-divisors = <1 2 4 0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
usb: usbck {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
- u-boot,dm-pre-reloc;
+ bootph-all;
pioA_clk: pioA_clk@2 {
#clock-cells = <0>;
reg = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioB_clk: pioB_clk@3 {
#clock-cells = <0>;
reg = <3>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioC_clk: pioC_clk@4 {
#clock-cells = <0>;
reg = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
usart0_clk: usart0_clk@6 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
aic: interrupt-controller@fffff000 {
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
atmel,clk-output-range = <0 120000000>;
atmel,clk-divisors = <1 2 4 0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
usb: usbck {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
- u-boot,dm-pre-reloc;
+ bootph-all;
pioA_clk: pioA_clk@2 {
#clock-cells = <0>;
reg = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioB_clk: pioB_clk@3 {
#clock-cells = <0>;
reg = <3>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioCDE_clk: pioCDE_clk@4 {
#clock-cells = <0>;
reg = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
usart0_clk: usart0_clk@7 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioB: gpio@fffff400 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioC: gpio@fffff600 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioD: gpio@fffff800 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioE: gpio@fffffa00 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
dbgu: serial@ffffee00 {
chosen {
bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs";
stdout-path = "serial0:115200n8";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
memory {
ahb {
apb {
dbgu: serial@ffffee00 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
ahb {
apb {
hlcdc: hlcdc@f8038000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
compatible = "atmel,at91sam9g20", "atmel,at91sam9";
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &dbgu;
};
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
board {
pinctrl_pck0_as_mck: pck0_as_mck {
atmel,pins =
};
&watchdog {
- u-boot,dm-pre-reloc;
+ bootph-all;
timeout-sec = <15>;
status = "okay";
};
/ {
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &dbgu;
};
};
dbgu: serial@fffff200 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
// SPDX-License-Identifier: GPL-2.0+
&dbgu {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
hlcdc: hlcdc@f8038000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &dbgu;
};
ahb {
apb {
dbgu: serial@ffffee00 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
ahb {
- u-boot,dm-pre-reloc;
+ bootph-all;
fb@0x00500000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
display-timings {
rev1 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
aic: interrupt-controller@fffff000 {
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
main_osc: main_osc {
compatible = "atmel,at91rm9200-clk-main-osc";
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
atmel,clk-output-range = <0 133333333>;
atmel,clk-divisors = <1 2 4 3>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
usb: usbck {
0xfffff800 0x200
0xfffffa00 0x200
>;
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,mux-mask = <
/* A B */
};
dbgu {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
chosen {
bootargs = "mem=64M root=/dev/mtdblock1 rw rootfstype=jffs2";
stdout-path = "serial0:115200n8";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
memory {
apb {
dbgu: serial@ffffee00 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
usart1: serial@fff90000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
aic: interrupt-controller@fffff000 {
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
main_rc_osc: main_rc_osc {
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
atmel,clk-output-range = <0 133333333>;
atmel,clk-divisors = <1 2 4 3>;
atmel,master-clk-have-div3-pres;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
usb: usbck {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
- u-boot,dm-pre-reloc;
+ bootph-all;
pioAB_clk: pioAB_clk@2 {
#clock-cells = <0>;
reg = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioCD_clk: pioCD_clk@3 {
#clock-cells = <0>;
reg = <3>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
fuse_clk: fuse_clk@4 {
0xfdffffff 0x07c00000 0xb83fffff /* pioC */
0x003fffff 0x003f8000 0x00000000 /* pioD */
>;
- u-boot,dm-pre-reloc;
+ bootph-all;
/* shared pinctrl settings */
dbgu {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioB: gpio@fffff600 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioC: gpio@fffff800 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioD: gpio@fffffa00 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
dbgu: serial@fffff200 {
chosen {
bootargs = "root=/dev/mtdblock1 rw rootfstype=jffs2";
stdout-path = "serial0:115200n8";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
memory {
ahb {
apb {
dbgu: serial@fffff200 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
fb0: fb@00500000 {
compatible = "atmel,at91sam9rl-lcdc";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
tcb0: timer@fffa0000 {
compatible = "atmel,at91rm9200-tcb";
<0xffffffff 0x0000c780>, /* pioB */
<0xffffffff 0xe3ffff0e>, /* pioC */
<0x003fffff 0x0001ff3c>; /* pioD */
- u-boot,dm-pre-reloc;
+ bootph-all;
/* shared pinctrl settings */
adc0 {
};
dbgu {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioB: gpio@fffff600 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioC: gpio@fffff800 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioD: gpio@fffffa00 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioD_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pmc: pmc@fffffc00 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
main: mainck {
compatible = "atmel,at91rm9200-clk-main";
clocks = <&clk32k>, <&main>, <&plla>, <&utmi>;
atmel,clk-output-range = <0 94000000>;
atmel,clk-divisors = <1 2 4 0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
prog: progck {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
- u-boot,dm-pre-reloc;
+ bootph-all;
pioA_clk: pioA_clk@2 {
#clock-cells = <0>;
reg = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioB_clk: pioB_clk@3 {
#clock-cells = <0>;
reg = <3>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioC_clk: pioC_clk@4 {
#clock-cells = <0>;
reg = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioD_clk: pioD_clk@5 {
#clock-cells = <0>;
reg = <5>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
usart0_clk: usart0_clk@6 {
chosen {
bootargs = "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=5 rw";
stdout-path = "serial0:115200n8";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
memory {
};
dbgu: serial@fffff200 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
status = "okay";
};
hlcdc: hlcdc@f8038000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
aic: interrupt-controller@fffff000 {
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
main_rc_osc: main_rc_osc {
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
atmel,clk-output-range = <0 133333333>;
atmel,clk-divisors = <1 2 4 3>;
atmel,master-clk-have-div3-pres;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
- u-boot,dm-pre-reloc;
+ bootph-all;
pioAB_clk: pioAB_clk@2 {
0xfffff800 0x200 /* pioC */
0xfffffa00 0x200 /* pioD */
>;
- u-boot,dm-pre-reloc;
+ bootph-all;
/* shared pinctrl settings */
dbgu {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb888>;
display-timings {
- u-boot,dm-pre-reloc;
+ bootph-all;
800x480 {
clock-frequency = <24000000>;
hactive = <800>;
vfront-porch = <22>;
vback-porch = <21>;
vsync-len = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
chosen {
bootargs = "root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
stdout-path = "serial0:115200n8";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ahb {
};
dbgu: serial@fffff200 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&uart0 {
skip-init;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
skip-init;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0_gpio14 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1_gpio14 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
clocks {
- u-boot,dm-pre-reloc;
+ bootph-all;
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
};
clocks: clocks {
- u-boot,dm-pre-reloc;
+ bootph-all;
periph_clk: periph-clk {
compatible = "fixed-clock";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
};
clocks: clocks {
- u-boot,dm-pre-reloc;
+ bootph-all;
periph_clk:periph-clk {
compatible = "fixed-clock";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
};
clocks {
- u-boot,dm-pre-reloc;
+ bootph-all;
periph_clk: periph_clk {
compatible = "fixed-clock";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
disable-wp;
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
uart0: serial@0xf4329148 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "cortina,ca-uart";
reg = <0x0 0xf4329148 0x30>;
status = "okay";
/ {
soc@1c00000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
nand {
};
panel {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&mmc0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&serial2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&spi1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
soc@1c00000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
nand {
};
&mmc0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&serial2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/ {
ocp {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&mmc2_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_pins_hs {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_pins_ddr_rev20 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_pins_hs200 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_iodelay_hs200_rev20_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&omap_dwc3_1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
dr_mode = "peripheral";
};
&usb2_phy1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb3_phy1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
fs_loader0: fs_loader@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "u-boot,fs-loader";
phandlepart = <&mmc1 1>;
};
#address-cells = <2>;
#size-cells = <2>;
ranges;
- u-boot,dm-spl;
+ bootph-pre-ram;
ipu2_memory_region: ipu2-memory@95800000 {
compatible = "shared-dma-pool";
reg = <0x0 0x95800000 0x0 0x3800000>;
reusable;
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
ipu1_memory_region: ipu1-memory@9d000000 {
reg = <0x0 0x9d000000 0x0 0x2000000>;
reusable;
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
ipu1_pgtbl: ipu1-pgtbl@95700000 {
reg = <0x0 0x95700000 0x0 0x40000>;
no-map;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
ipu2_pgtbl: ipu2-pgtbl@95740000 {
reg = <0x0 0x95740000 0x0 0x40000>;
no-map;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&timer3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&timer4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&timer7 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&timer8 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&timer9 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&timer11 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmu_ipu1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmu_ipu2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ipu1 {
status = "okay";
memory-region = <&ipu1_memory_region>;
pg-tbl = <&ipu1_pgtbl>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ipu2 {
status = "okay";
memory-region = <&ipu2_memory_region>;
pg-tbl = <&ipu2_pgtbl>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&l4_wkup {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&prm {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ipu1_rst {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ipu2_rst {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&mmc2_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_pins_hs {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_pins_ddr_rev20 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_iodelay_ddr_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_pins_hs200 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_iodelay_hs200_rev20_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&omap_dwc3_1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
dr_mode = "peripheral";
};
&usb2_phy1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb3_phy1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&mmc2_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_pins_hs {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_pins_ddr_rev20 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_iodelay_ddr_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_pins_hs200 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_iodelay_hs200_rev20_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&omap_dwc3_1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
dr_mode = "peripheral";
};
&usb2_phy1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb3_phy1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "omap5-u-boot.dtsi"
&omap_dwc3_1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
dr_mode = "peripheral";
};
&usb2_phy1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb3_phy1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&mmc2_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_pins_hs200 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2_iodelay_hs200_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&omap_dwc3_1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
dr_mode = "peripheral";
};
&usb2_phy1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb3_phy1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/ {
smem {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl@1000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
uart {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
qcom,gcc@1800000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
serial@78b0000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
/ {
smem {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl@1010000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
uart {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
clock-controller@300000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
serial@75b0000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
/
{
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
serial@a84000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
clock-controller@100000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pinctrl_north@3900000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
};
fimd@14400000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "samsung,exynos-fimd";
reg = <0x14400000 0x10000>;
#address-cells = <1>;
compatible = "samsung,exynos4210-uart";
reg = <0x12C30000 0x100>;
interrupts = <0 54 0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
id = <3>;
};
};
};
adc@12D10000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
vdd-supply = <&ldo4_reg>;
status = "okay";
};
fin_pll: xxti {
compatible = "fixed-clock";
clock-output-names = "fin_pll";
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
};
clock_topc: clock-controller@10570000 {
compatible = "samsung,exynos7-clock-topc";
reg = <0x10570000 0x10000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <1>;
clocks = <&fin_pll>;
clock-names = "fin_pll";
clock_top0: clock-controller@105d0000 {
compatible = "samsung,exynos7-clock-top0";
reg = <0x105d0000 0xb000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <1>;
clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
<&clock_topc DOUT_SCLK_BUS1_PLL>,
clock_peric1: clock-controller@14c80000 {
compatible = "samsung,exynos7-clock-peric1";
reg = <0x14c80000 0xd00>;
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <1>;
clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
<&clock_top0 CLK_SCLK_UART1>,
pinctrl@13470000 {
compatible = "samsung,exynos7420-pinctrl";
reg = <0x13470000 0x1000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
serial2_bus: serial2-bus {
samsung,pins = "gpd1-4", "gpd1-5";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
serial@14C30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x14C30000 0x100>;
- u-boot,dm-pre-reloc;
+ bootph-all;
clocks = <&clock_peric1 PCLK_UART2>,
<&clock_peric1 SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
fin_pll: xxti {
compatible = "fixed-clock";
clock-output-names = "fin_pll";
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
};
compatible = "fixed-clock";
clock-output-names = "fin_uart";
clock-frequency = <132710400>;
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
};
uart2: serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
- u-boot,dm-pre-reloc;
+ bootph-all;
clocks = <&fin_uart>, <&fin_uart>; // driver uses 1st clock
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
*/
&mu {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&clk {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&iomuxc {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio0 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio1 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio2 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio3 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio4 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio5 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio6 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio7 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_dma {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_dma_lpuart1 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_conn {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_conn_sdch0 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_conn_sdch1 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_conn_sdch2 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio0 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio1 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio2 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio3 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio4 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio5 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio6 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio7 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&lpuart0 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&lpuart1 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&lpuart2 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&lpuart3 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&usdhc1 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&usdhc2 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&usdhc3 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&{/imx8qm-pm} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mu {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&clk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio7 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn_sdch0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn_sdch1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn_sdch2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_dma {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_dma_lpuart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_caam {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_caam_jr1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_caam_jr2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_caam_jr3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio7 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&lpuart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
mmc-hs400-1_8v;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&crypto {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/imx8qx-pm} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mu {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&clk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio7 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn_sdch0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn_sdch1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn_sdch2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio7 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&lpuart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/imx8qx-pm} {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&mu {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&clk {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&iomuxc {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio0 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio1 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio2 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio3 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio4 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio5 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio6 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_lsio_gpio7 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_dma {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_dma_lpuart0 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_dma_lpuart3 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_conn {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_conn_sdch0 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_conn_sdch1 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pd_conn_sdch2 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio0 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio1 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio2 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio3 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio4 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio5 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio6 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&gpio7 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&lpuart3 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&usdhc1 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&usdhc2 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&{/imx8qx-pm} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mu {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&clk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio7 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn_sdch0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn_sdch1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn_sdch2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_dma {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_dma_lpuart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_caam {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_caam_jr1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_caam_jr2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_caam_jr3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio7 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&lpuart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
mmc-hs400-1_8v;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&crypto {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&A35_0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&lpuart0 {
#endif
&fspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
flash@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&dspi2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&esdhc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&esdhc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&lpuart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&duart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/*
};
&soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sysclk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&i2c0 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
fpga@66 {
#address-cells = <1>;
&i2c0 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
i2c-mux@77 {
compatible = "nxp,pca9547";
&i2c0 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
pca9547@75 {
compatible = "nxp,pca9547";
&i2c0 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
fpga@66 {
#address-cells = <1>;
&i2c0 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&i2c4 {
*/
&dwmmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
*/
&mmc0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
axi {
- u-boot,dm-pre-reloc;
+ bootph-all;
ahb@c0000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
spi0: spi@200 {
compatible = "hpe,gxp-spi";
#include "imx28-u-boot.dtsi"
/ {
apb@80000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
apbh@80000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
apbx@80040000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ssp0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ssp3 {
num-cs = <2>;
spi-max-frequency = <40000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/ {
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
bus@50000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&gpio1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio6 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio7 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&gpio1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
vbus1_regulator: regulator@1 {
- u-boot,dm-preloc;
+ bootph-all;
compatible = "regulator-fixed";
regulator-name = "vbus1_regulator";
regulator-min-microvolt = <5000000>;
};
&uart1 {
- u-boot,dm-spl;
- u-boot,dm-preloc;
+ bootph-pre-ram;
+ bootph-all;
status = "okay";
};
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
};
};
&ecspi1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>;
status = "okay";
spi-max-frequency = <25000000>;
m25p32@1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p", "jedec,spi-nor";
&wdog1 {
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx6qdl-icore-u-boot.dtsi"
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx6qdl-u-boot.dtsi"
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
bus@2000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
spba-bus@2000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
bus@2100000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio7 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
bus@2100000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&uart5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#include "imx6qdl-icore-u-boot.dtsi"
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/ {
clocks {
- u-boot,dm-spl;
+ bootph-pre-ram;
osc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&clks {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx6qdl-u-boot.dtsi"
&uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx6qdl-u-boot.dtsi"
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ecspi1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_ecspi1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&m25p80 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpmi {
// SPDX-License-Identifier: GPL-2.0+
&{/soc/bus@2000000} { /* AIPS1 */
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&{/soc} {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &uart2;
};
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_gpio {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&aips2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&backlight {
* because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot
*/
&gpio2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
wp_spi_nor {
gpio-hog;
};
&gpio3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&ecspi4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&flash {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_ecspi4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &uart2;
};
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_gpio {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&iomuxc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&aips2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&backlight {
* because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot
*/
&gpio2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
wp_spi_nor {
gpio-hog;
};
&gpio4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&ecspi1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&flash {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_ecspi1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &uart1;
};
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_gpio {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&iomuxc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&aips1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&backlight {
* because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot
*/
&gpio2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
wp_spi_nor {
gpio-hog;
};
&gpio4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&ecspi1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&flash {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_ecspi1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&aips1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_microsom_uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio6 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usdhc1 {
};
&usdhc2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usdhc3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#include "imx6qdl-u-boot.dtsi"
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx6qdl-u-boot.dtsi"
&soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&aips1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
no-1-8-v;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
soc {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
bus@2000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
spba-bus@2000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
bus@2100000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ipu1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
*/
&pinctrl_uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&pinctrl_uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
*/
&{/aliases} {
- u-boot,dm-pre-reloc;
+ bootph-all;
display0 = &lcdif;
};
&soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&aips2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&iomuxc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&lcdif {
display = <&display0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
display0: display@0 {
bits-per-pixel = <24>;
#include "imx6ul-u-boot.dtsi"
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&iomuxc {
pinctrl_usdhc1: usdhc1grp {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
#include "imx6ul-isiot-u-boot.dtsi"
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx6ul-u-boot.dtsi"
&soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&aips1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/ {
soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&aips2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&aips1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
spba-bus@02000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&lcdif {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&pinctrl_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/ {
soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&aips1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&aips2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
*/
&pinctrl_uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
aliases {
- u-boot,dm-pre-reloc;
+ bootph-all;
usb0 = &usbotg1; /* required for ums */
display0 = &lcdif;
};
};
&pinctrl_uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_uart1_ctrl1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&lcdif {
&pinctrl_lcdif_ctrl>;
status = "okay";
display = <&display0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
display0: display0 {
bits-per-pixel = <18>;
display-timings {
native-mode = <&timing_vga>;
timing_vga: 640x480 {
- u-boot,dm-pre-reloc;
+ bootph-all;
clock-frequency = <25175000>;
hactive = <640>;
vactive = <480>;
};
&gpio1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpmi {
scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
eeprom_som: eeprom@50 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "atmel,24c04";
reg = <0x50>;
status = "okay";
};
pinctrl_i2c2: i2cgrp {
- u-boot,dm-pre-reloc;
+ bootph-all;
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
};
pinctrl_i2c2_gpio: i2c2grp_gpio {
- u-boot,dm-pre-reloc;
+ bootph-all;
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
*/
&pinctrl_uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpmi {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
&usdhc1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
&usdhc2 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
*/
&pinctrl_uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpmi {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
&usdhc1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
&usdhc2 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
/ {
soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&aips1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&aips2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&aips3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
*/
&pinctrl_uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
*/
&{/soc} {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&aips2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&iomuxc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&iomuxc_snvs {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpmi {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
display = <&display0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
display0: display0 {
bits-per-pixel = <18>;
pinctrl-0 = <&pinctrl_lcdif>;
status = "okay";
display = <&display0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
display0: display {
bits-per-pixel = <16>;
};
&aips3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
*/
&iomuxc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ahbbridge0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ahbbridge1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&lpuart4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbotg1 {
extcon = <&usbphy1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbphy1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio_ptc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
*/
&soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&ahbbridge0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&ahbbridge1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&iomuxc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&iomuxc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&lpuart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&lpuart5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&lpuart6 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&lpuart7 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&aips4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
®_usdhc2_vmmc {
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pca6416_0 {
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
®_usbotg1 {
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbmisc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbotg1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbphynop1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
- u-boot,dm-spl;
+ bootph-pre-ram;
wdt = <&wdog1>;
};
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&binman_fip {
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
- u-boot,dm-spl;
+ bootph-pre-ram;
wdt = <&wdog1>;
};
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&fec1 {
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&buck4_reg {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&buck5_reg {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_hog_sbc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
regulators {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbotg1 {
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
firmware {
};
&aips4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
®_usdhc2_vmmc {
};
&pinctrl_reg_usdhc2_vmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&crypto {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbmisc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbphynop1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbotg1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
fsl,signal-voltage-switch-extra-delay-ms = <8>;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&fec1 {
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx8mm-icore-mx8mm-u-boot.dtsi"
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc1_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx8mm-icore-mx8mm-u-boot.dtsi"
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc1_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx8mm-u-boot.dtsi"
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3_100mhz {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3_200mhz {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
firmware {
};
&crypto {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
&i2c2 {
};
&pinctrl_ecspi1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart3 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
&pinctrl_usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc1_100mhz {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc1_200mhz {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pca9450 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ecspi1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart3 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&aips4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c4 {
};
®_usb_otg1_vbus {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbmisc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbphynop1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbotg1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
firmware {
};
&aips4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
®_usdhc2_vmmc {
};
&pinctrl_reg_usdhc2_vmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbmisc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbphynop1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbotg1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
/*
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&soc {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
+ bootph-all;
+ bootph-pre-ram;
};
&aips1 {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
+ bootph-all;
+ bootph-pre-ram;
};
&aips2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&aips3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&binman {
};
&clk {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
+ bootph-all;
+ bootph-pre-ram;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&osc_24m {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
+ bootph-all;
+ bootph-pre-ram;
};
&spba1 {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
+ bootph-all;
+ bootph-pre-ram;
};
&spba2 {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
+ bootph-all;
+ bootph-pre-ram;
};
};
&pinctrl_fec1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@69} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@69/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&pinctrl_fec1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&pinctrl_fec1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&pinctrl_fec1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&pinctrl_fec1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gsc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
- u-boot,dm-spl;
+ bootph-pre-ram;
wdt = <&wdog1>;
};
};
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&binman_uboot {
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
eeprom_module: eeprom@50 {
compatible = "i2c-eeprom";
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx8mn-u-boot.dtsi"
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pca6416_0 {
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
®_usdhc2_vmmc {
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx8mn-u-boot.dtsi"
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx8mn-bsh-smm-s2-u-boot-common.dtsi"
&pinctrl_gpmi_nand {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpmi {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx8mn-bsh-smm-s2-u-boot-common.dtsi"
&pinctrl_usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx8mn-u-boot.dtsi"
&pinctrl_reg_usdhc2_vmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
®_usdhc2_vmmc {
};
&pinctrl_uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&crypto {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
};
#include "imx8mn-ddr4-evk-u-boot.dtsi"
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
+ bootph-all;
+ bootph-pre-ram;
};
&aips1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
&aips2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&aips3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&aips4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&clk {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&osc_24m {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
&spba1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&binman {
#include "imx8mn-u-boot.dtsi"
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_reg_usdhc2_vmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&pinctrl_fec1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx8mn-u-boot.dtsi"
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gsc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&buck4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&buck5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&eqos {
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c3_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_100mhz {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_200mhz {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_vmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3_100mhz {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3_100mhz {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
regulators {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
®_usdhc2_vmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/* SDIO WiFi */
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
firmware {
optee {
};
®_usdhc2_vmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&crypto {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&eqos {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
firmware {
};
®_usdhc2_vmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&crypto {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
no-1-8-v;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&eqos {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
®_usdhc2_vmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
®_usdhc2_vmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_pins {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
firmware {
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
®_usdhc2_vmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_pmic {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
sd-uhs-sdr104;
sd-uhs-ddr50;
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
};
&soc {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
+ bootph-all;
+ bootph-pre-ram;
};
&clk {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&osc_32k {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
&osc_24m {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
&aips1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
&aips2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&aips3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&binman {
wdt-reboot {
compatible = "wdt-reboot";
- u-boot,dm-spl;
+ bootph-pre-ram;
wdt = <&wdog1>;
};
};
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
dio0_hog {
gpio-hog;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
pcie1_wdis_hog {
gpio-hog;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
m2_dis2_hog {
gpio-hog;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
m2_dis1_hog {
gpio-hog;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
rs485_half {
gpio-hog;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&switch {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
sd-uhs-ddr50;
sd-uhs-sdr104;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gsc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
- u-boot,dm-spl;
+ bootph-pre-ram;
wdt = <&wdog1>;
};
};
};
&clk {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
+ bootph-all;
+ bootph-pre-ram;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&crypto {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&eqos {
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
regulator-ethphy {
gpio-hog;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
eeprom_module: eeprom@50 {
compatible = "i2c-eeprom";
};
&i2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c4 {
};
&pca9450 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_pwr_en {
- u-boot,dm-spl;
+ bootph-pre-ram;
u-boot,off-on-delay-us = <20000>;
};
&pinctrl_uart3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_cd {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
®_usdhc2_vmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
sd-uhs-ddr50;
sd-uhs-sdr104;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&pinctrl_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&binman {
#include "imx8mq-u-boot.dtsi"
&pinctrl_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
};
&uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx8mq-u-boot.dtsi"
&pinctrl_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart1 { /* console */
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&binman {
};
&uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "imx8mq-u-boot.dtsi"
&pinctrl_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&aips1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&aips2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&aips3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&aips4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&binman {
&{/imx8qx-pm} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mu {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&clk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_lsio_gpio7 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_dma {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_dma_lpuart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_dma_lpuart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn_sdch0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn_sdch1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pd_conn_sdch2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio7 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&lpuart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&lpuart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
compatible = "fsl,imx8ulp-mu";
reg = <0 0x27020000 0 0x10000>;
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&per_bridge3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&per_bridge4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&iomuxc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
fsl,mux_mask = <0xf00>;
};
&pinctrl_lpuart5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&lpuart5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog3>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
aliases {
};
&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
+ bootph-all;
+ bootph-pre-ram;
};
&aips1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
&aips2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&aips3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
®_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_reg_usdhc2_vmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&lpuart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
fsl,signal-voltage-switch-extra-delay-ms = <8>;
};
&lpi2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_lpi2c2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&fec {
};
&s4muap {
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
};
/ {
chosen {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
clocks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&osc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&anatop {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpt1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&lpuart1 { /* console */
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&semc {
- u-boot,dm-spl;
+ bootph-pre-ram;
bank1: bank@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
imxrt1020-evk {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl_semc: semcgrp {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pinctrl_usdhc0: usdhc0grp {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&pinctrl_lpuart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
chosen {
- u-boot,dm-spl;
+ bootph-pre-ram;
tick-timer = &gpt;
};
clocks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
usbphy1: usbphy@400d9000 {
compatible = "fsl,imxrt-usbphy";
};
&semc {
- u-boot,dm-spl;
+ bootph-pre-ram;
/*
* Memory configuration from sdram datasheet IS42S16160J-6BLI
*/
bank1: bank@0 {
fsl,base-address = <0x80000000>;
fsl,memory-size = <MEM_SIZE_32M>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&osc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&anatop {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpt {
clocks = <&osc>;
compatible = "fsl,imxrt-gpt";
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&lpuart1 { /* console */
compatible = "fsl,imxrt-lpuart";
clock-names = "per";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "fsl,imxrt-iomuxc";
pinctrl-0 = <&pinctrl_lpuart1>;
MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
(IMX_PAD_SION | 0xf1) /* SEMC_DQS */
>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pinctrl_lcdif: lcdifgrp {
};
pinctrl_lpuart1: lpuart1grp {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pinctrl_usdhc0: usdhc0grp {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&usdhc1 {
compatible = "fsl,imxrt-usdhc";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&lcdif {
/ {
chosen {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
clocks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&osc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&rcosc16M {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&osc32k {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpt1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&lpuart1 { /* console */
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&semc {
- u-boot,dm-spl;
+ bootph-pre-ram;
bank1: bank@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&iomuxc {
- u-boot,dm-spl;
+ bootph-pre-ram;
imxrt1170-evk {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl_lpuart1: lpuart1grp {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pinctrl_usdhc0: usdhc0grp {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pinctrl_semc: semcgrp {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&usdhc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
reserved-memory {
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
dm_tifs: dm-tifs {
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
compatible = "ti,j721e-esm";
reg = <0x0 0x4100000 0x0 0x1000>;
ti,esm-pins = <0>, <1>, <2>, <85>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_main {
sa3_secproxy: secproxy@44880000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "rt", "scfg", "target_data";
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>;
mbox-names = "tx", "rx", "boot_notify";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
main_esm: esm@420000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x420000 0x0 0x1000>;
ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&mcu_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
wkup_uart0_pins_default: wkup-uart0-pins-default {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6) WKUP_UART0_CTSn */
AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
main_uart1_pins_default: main-uart1-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/* Main UART1 is used for TIFS firmware logs */
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ospi0 {
};
memory@80000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_main{
- u-boot,dm-spl;
+ bootph-pre-ram;
timer1: timer@2400000 {
compatible = "ti,omap5430-timer";
reg = <0x00 0x2400000 0x00 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&dmss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&secure_proxy_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dmsc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_pds {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_reset {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&chipid {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_uart0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cbass_mcu {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cbass_wakeup {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdhci1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_mmc1_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&fss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ospi0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ospi0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
flash@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
partitions {
- u-boot,dm-spl;
+ bootph-pre-ram;
partition@3fc0000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
<0x0 0x43000200 0x0 0x8>;
reg-names = "cpsw_nuss", "mac_efuse";
/delete-property/ ranges;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpsw-phy-sel@04044 {
compatible = "ti,am64-phy-gmii-sel";
reg = <0x0 0x00104044 0x0 0x8>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cpsw_port1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cpsw_port2 {
<&k3_pds 55 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 170 1>, <&k3_clks 16 4>;
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,ctl-data = <
DDRSS_CTL_0_DATA
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x00000000 0x80000000>; /* 2G RAM */
- u-boot,dm-spl;
+ bootph-pre-ram;
};
reserved-memory {
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
dm_tifs: dm-tifs {
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
<0x0 0x44860000 0x0 0x20000>,
<0x0 0x43600000 0x0 0x10000>;
reg-names = "rt", "scfg", "target_data";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
sysctrler: sysctrler {
<&secure_proxy_main 0>,
<&sa3_secproxy 0>;
mbox-names = "tx", "rx", "boot_notify";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&mcu_pmx0 {
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
wkup_uart0_pins_default: wkup-uart0-pins-default {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4) WKUP_UART0_RXD */
AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */
>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
main_uart1_pins_default: main-uart1-pins-default {
pinctrl-single,pins = <
AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */
AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */
AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */
>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/* Main UART1 is used for TIFS firmware logs */
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
memory@80000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_main{
- u-boot,dm-spl;
+ bootph-pre-ram;
timer1: timer@2400000 {
compatible = "ti,omap5430-timer";
reg = <0x00 0x2400000 0x00 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&dmss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&secure_proxy_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dmsc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_pds {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_reset {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&chipid {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_uart0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cbass_mcu {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cbass_wakeup {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_i2c0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_i2c1_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&exp1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdhci1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_mmc1_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_reset {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dmsc {
- u-boot,dm-spl;
+ bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&vdd_mmc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,ctl-data = <
DDRSS_CTL_0_DATA
};
memory@80000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_main{
- u-boot,dm-spl;
+ bootph-pre-ram;
timer1: timer@2400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x2400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <200000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
chipid@14 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
main_i2c0_pins_default: main-i2c0-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
&main_i2c0 {
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb0 {
dr_mode="peripheral";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbss0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_mmc1_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_usb0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dmss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&secure_proxy_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dmsc {
- u-boot,dm-spl;
+ bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&k3_pds {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_reset {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdhci0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdhci1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cpsw3g {
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
a53_0: a53@0 {
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
reserved-memory {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
vtt_supply: vtt-supply {
regulator-max-microvolt = <3300000>;
gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
states = <0 0x0 3300000 0x1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
mbox-names = "tx", "rx";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
compatible = "ti,j721e-esm";
reg = <0x0 0x420000 0x0 0x1000>;
ti,esm-pins = <160>, <161>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_mcu {
- u-boot,dm-spl;
+ bootph-pre-ram;
mcu_esm: esm@4100000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x4100000 0x0 0x1000>;
ti,esm-pins = <0>, <1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
main_uart0_pins_default: main-uart0-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
};
main_uart1_pins_default: main-uart1-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
};
main_mmc0_pins_default: main-mmc0-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
};
main_mmc1_pins_default: main-mmc1-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
};
ddr_vtt_pins_default: ddr-vtt-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
>;
};
&main_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
};
&main_gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
/delete-property/ power-domains;
};
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
a53_0: a53@0 {
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
reserved-memory {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
mbox-names = "tx", "rx";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
compatible = "ti,j721e-esm";
reg = <0x0 0x420000 0x0 0x1000>;
ti,esm-pins = <160>, <161>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_mcu {
- u-boot,dm-spl;
+ bootph-pre-ram;
mcu_esm: esm@4100000 {
compatible = "ti,j721e-esm";
reg = <0x0 0x4100000 0x0 0x1000>;
ti,esm-pins = <0>, <1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
main_uart0_pins_default: main-uart0-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
};
main_uart1_pins_default: main-uart1-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
};
main_mmc1_pins_default: main-mmc1-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
};
main_usb0_pins_default: main-usb0-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
&main_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
};
memory@80000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_main{
- u-boot,dm-spl;
+ bootph-pre-ram;
timer1: timer@2400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x2400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <200000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
chipid@14 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
main_i2c0_pins_default: main-i2c0-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
};
&main_i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dmss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&secure_proxy_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dmsc {
- u-boot,dm-spl;
+ bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&k3_pds {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_reset {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdhci0 {
status = "disabled";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdhci1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_mmc1_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cpsw3g {
<0x0 0x43000200 0x0 0x8>;
reg-names = "cpsw_nuss", "mac_efuse";
/delete-property/ ranges;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpsw-phy-sel@04044 {
compatible = "ti,am64-phy-gmii-sel";
reg = <0x0 0x43004044 0x0 0x8>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
ethernet-ports {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cpsw_port2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_bcdma {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_pktdma {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&rgmii1_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&rgmii2_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mdio1_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cpsw3g_phy1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_usb0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&serdes_ln_ctrl {
};
&usbss0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb0 {
dr_mode = "host";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&serdes_wiz0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&serdes0_usb_link {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&serdes0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&serdes_refclk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
leds {
- u-boot,dm-spl;
+ bootph-pre-ram;
status-led-red {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
status-led-green {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&cbass_mcu {
- u-boot,dm-spl;
+ bootph-pre-ram;
mcu_navss: bus@28380000 {
ringacc@2b800000 {
};
&cbass_wakeup {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cbass_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
main_navss: bus@30800000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&wkup_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
mcu-fss0-ospi0-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
main-uart1-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
current-speed = <115200>;
};
&wkup_gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ospi0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
flash@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&secure_proxy_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dmsc {
- u-boot,dm-spl;
+ bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&k3_pds {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_reset {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&fss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
<&k3_pds 244 TI_SCI_PD_SHARED>;
assigned-clocks = <&k3_clks 20 1>;
assigned-clock-rates = <DDR_PLL_FREQUENCY>;
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,ss-reg = <
DDRSS_V2H_CTL_REG
};
&cbass_main{
- u-boot,dm-spl;
+ bootph-pre-ram;
main_navss: bus@30800000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_mcu {
- u-boot,dm-spl;
+ bootph-pre-ram;
mcu_navss: bus@28380000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
ringacc@2b800000 {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,dma-ring-reset-quirk;
};
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&cbass_wakeup {
- u-boot,dm-spl;
+ bootph-pre-ram;
chipid@43000014 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&secure_proxy_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dmsc {
- u-boot,dm-spl;
+ bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&k3_pds {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_reset {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
wkup_i2c0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
usb0_pins_default: usb0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_uart0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_pmx1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_pmx0 {
mcu-fss0-ospi0-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_mmc0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_mmc1_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdhci0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdhci1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&davinci_mdio {
};
&wkup_i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb1 {
};
&fss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ospi0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
flash@0{
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&dwc3_0 {
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb0_phy {
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins_default>;
dr_mode = "peripheral";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&scm_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
vtt_supply: vtt_supply {
regulator-max-microvolt = <3300000>;
gpios = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
states = <0 0x0 3300000 0x1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
<0x0 0x2a480000 0x0 0x80000>;
reg-names = "rt", "scfg", "target_data";
#mbox-cells = <1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&wkup_gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cbass_wakeup {
compatible = "ti,am654-system-controller";
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
clk_200mhz: dummy_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&wkup_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
};
&mcu_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&mcu_uart0_pins_default>;
clock-frequency = <48000000>;
compatible = "ti,am654-vtm", "ti,am654-avs";
vdd-supply-3 = <&vdd_mpu>;
vdd-supply-4 = <&vdd_mpu>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
wkup_uart0_pins_default: wkup_uart0_pins_default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wkup_vtt_pins_default: wkup_vtt_pins_default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
mcu_uart0_pins_default: mcu_uart0_pins_default {
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
main_uart0_pins_default: main-uart0-pins-default {
pinctrl-single,pins = <
AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
main_mmc0_pins_default: main_mmc0_pins_default {
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
main_mmc1_pins_default: main_mmc1_pins_default {
AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
vdd_mpu: tps62363@60 {
compatible = "ti,tps62363";
regulator-boot-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
usb0_pins_default: usb0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&dwc3_0 {
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
/delete-property/ clocks;
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
&usb0_phy {
status = "okay";
- u-boot,dm-spl;
+ bootph-pre-ram;
/delete-property/ clocks;
};
pinctrl-names = "default";
pinctrl-0 = <&usb0_pins_default>;
dr_mode = "peripheral";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&scm_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&wkup_i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cbass_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_navss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cbass_mcu_wakeup {
- u-boot,dm-spl;
+ bootph-pre-ram;
timer1: timer@40400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <250000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
chipid@43000014 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&mcu_navss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_ringacc {
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_udmap {
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&secure_proxy_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sms {
- u-boot,dm-spl;
+ bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_uart8_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_mmc1_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_pds {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_reset {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_uart8 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_cpsw {
};
&main_sdhci1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
fs_loader0: fs_loader@0 {
compatible = "u-boot,fs-loader";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
a72_0: a72@0 {
ti,sci = <&sms>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
clk_200mhz: dummy_clock_200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
clk_19_2mhz: dummy_clock_19_2mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_mcu_wakeup {
sa3_secproxy: secproxy@44880000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "ti,am654-secure-proxy";
reg = <0x0 0x44880000 0x0 0x20000>,
<0x0 0x44860000 0x0 0x20000>,
<0x0 0x2a480000 0x0 0x80000>;
reg-names = "rt", "scfg", "target_data";
#mbox-cells = <1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
mbox-names = "tx", "rx", "boot_notify";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
dm_tifs: dm-tifs {
mbox-names = "rx", "tx";
mboxes= <&mcu_secproxy 21>,
<&mcu_secproxy 23>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&wkup_pmx0 {
mcu_uart0_pins_default: mcu-uart0-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /*(C24) WKUP_GPIO0_13.MCU_UART0_RXD*/
J721S2_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /*(C25) WKUP_GPIO0_12.MCU_UART0_TXD*/
};
wkup_uart0_pins_default: wkup-uart0-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /*(E25) WKUP_GPIO0_6.WKUP_UART0_CTSn*/
J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /*(F28) WKUP_GPIO0_7.WKUP_UART0_RTSn*/
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_uart0 {
};
&cbass_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_navss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cbass_mcu_wakeup {
- u-boot,dm-spl;
+ bootph-pre-ram;
timer1: timer@40400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <250000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
chipid@43000014 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
mcu_navss: bus@28380000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
#address-cells = <2>;
#size-cells = <2>;
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
dma-controller@285c0000 {
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&secure_proxy_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dmsc {
- u-boot,dm-spl;
+ bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&k3_pds {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_reset {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_sdhci0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_sdhci1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_i2c0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&exp2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_cpsw {
};
&main_usbss0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbss0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,usb2-only;
};
&usb0 {
dr_mode = "peripheral";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_fss0_hpb0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&fss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&hbmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
flash@0,0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&hbmc_mux {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&serdes_ln_ctrl {
};
&serdes0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_r5fss0 {
};
fs_loader0: fs_loader@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "u-boot,fs-loader";
};
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
clk_200mhz: dummy_clock_200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
clk_19_2mhz: dummy_clock_19_2mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_mcu_wakeup {
mcu_secproxy: secproxy@2a380000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "ti,am654-secure-proxy";
reg = <0x0 0x2a380000 0x0 0x80000>,
<0x0 0x2a400000 0x0 0x80000>,
};
sysctrler: sysctrler {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "ti,am654-system-controller";
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx";
mbox-names = "rx", "tx";
mboxes= <&mcu_secproxy 21>,
<&mcu_secproxy 23>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
wkup_vtm0: vtm@42040000 {
};
&wkup_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
wkup_uart0_pins_default: wkup_uart0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
};
mcu_uart0_pins_default: mcu_uart0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) WKUP_GPIO0_13.MCU_UART0_RXD */
J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) WKUP_GPIO0_12.MCU_UART0_TXD */
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
main_uart0_pins_default: main_uart0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
};
main_i2c0_pins_default: main-i2c0-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
};
&wkup_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
};
&wkup_i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
lp876441: lp876441@4c {
compatible = "ti,lp876441";
reg = <0x4c>;
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
regulators: regulators {
- u-boot,dm-spl;
+ bootph-pre-ram;
buck1_reg: buck1 {
/*VDD_CPU_AVS_REG*/
regulator-name = "buck1";
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&wkup_vtm0 {
vdd-supply-2 = <&buck1_reg>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_i2c0 {
};
&cbass_main{
- u-boot,dm-spl;
+ bootph-pre-ram;
main_navss: bus@30000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_mcu_wakeup {
- u-boot,dm-spl;
+ bootph-pre-ram;
timer1: timer@40400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <250000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
mcu_navss: bus@28380000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
ringacc@2b800000 {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
dma-controller@285c0000 {
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
chipid@43000014 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&secure_proxy_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dmsc {
- u-boot,dm-spl;
+ bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&k3_pds {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_reset {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_sdhci0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_sdhci1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wiz3_pll1_refclk {
};
&main_usbss0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbss0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb0 {
dr_mode = "peripheral";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_cpsw {
};
&main_mmc1_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_i2c0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_i2c0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&exp2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_fss0_ospi0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&fss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&hbmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
flash@0,0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&hbmc_mux {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ospi0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
flash@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&ospi1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
flash@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&mcu_fss0_hpb0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_gpio_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_fss0_ospi1_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_r5fss0 {
ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,ctl-data = <
DDRSS_CTL_00_DATA
};
fs_loader0: fs_loader@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "u-boot,fs-loader";
};
};
&tps659413a {
esm: esm {
compatible = "ti,tps659413-esm";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
clk_200mhz: dummy_clock_200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
clk_19_2mhz: dummy_clock_19_2mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_mcu_wakeup {
mcu_secproxy: secproxy@28380000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "ti,am654-secure-proxy";
reg = <0x0 0x2a380000 0x0 0x80000>,
<0x0 0x2a400000 0x0 0x80000>,
};
sysctrler: sysctrler {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "ti,am654-system-controller";
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx";
mbox-names = "rx", "tx";
mboxes= <&mcu_secproxy 21>,
<&mcu_secproxy 23>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
compatible = "ti,j721e-esm";
reg = <0x0 0x700000 0x0 0x1000>;
ti,esm-pins = <344>, <345>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&wkup_pmx0 {
wkup_uart0_pins_default: wkup_uart0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
};
mcu_uart0_pins_default: mcu_uart0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
};
mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
&main_pmx0 {
main_uart0_pins_default: main_uart0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
};
&wkup_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
};
&wkup_i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
tps659413a: tps659413a@48 {
reg = <0x48>;
compatible = "ti,tps659413";
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
regulators: regulators {
- u-boot,dm-spl;
+ bootph-pre-ram;
buck12_reg: buck12 {
/*VDD_CPU*/
regulator-name = "buck12";
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&wkup_vtm0 {
vdd-supply-2 = <&buck12_reg>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbss0 {
&ospi1 {
pinctrl-names = "default";
pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
- u-boot,dm-spl;
+ bootph-pre-ram;
reg = <0x0 0x47050000 0x0 0x100>,
<0x0 0x58000000 0x0 0x8000000>;
cdns,read-delay = <2>;
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
fs_loader0: fs_loader@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "u-boot,fs-loader";
};
};
&tps659412 {
esm: esm {
compatible = "ti,tps659413-esm";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
clk_200mhz: dummy_clock_200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
clk_19_2mhz: dummy_clock_19_2mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_mcu_wakeup {
mcu_secproxy: secproxy@28380000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "ti,am654-secure-proxy";
reg = <0x0 0x2a380000 0x0 0x80000>,
<0x0 0x2a400000 0x0 0x80000>,
};
sysctrler: sysctrler {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "ti,am654-system-controller";
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx";
mbox-names = "rx", "tx";
mboxes= <&mcu_secproxy 21>,
<&mcu_secproxy 23>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
compatible = "ti,j721e-esm";
reg = <0x0 0x700000 0x0 0x1000>;
ti,esm-pins = <344>, <345>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&wkup_pmx0 {
wkup_uart0_pins_default: wkup_uart0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
};
mcu_uart0_pins_default: mcu_uart0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */
J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */
&main_pmx0 {
main_uart0_pins_default: main_uart0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
};
&wkup_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
status = "okay";
};
&wkup_i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
tps659412: tps659412@48 {
reg = <0x48>;
compatible = "ti,tps659412";
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
regulators: regulators {
- u-boot,dm-spl;
+ bootph-pre-ram;
/* 3 Phase Buck */
buck123_reg: buck123 {
/* VDD_CPU */
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&wkup_vtm0 {
vdd-supply-2 = <&buck123_reg>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbss0 {
};
&cbass_main{
- u-boot,dm-spl;
+ bootph-pre-ram;
main_navss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_mcu_wakeup {
- u-boot,dm-spl;
+ bootph-pre-ram;
timer1: timer@40400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
mcu-navss {
- u-boot,dm-spl;
+ bootph-pre-ram;
ringacc@2b800000 {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
dma-controller@285c0000 {
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
chipid@43000014 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&secure_proxy_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dmsc {
- u-boot,dm-spl;
+ bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&k3_pds {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_reset {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_sdhci0 {
};
&main_sdhci1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wiz3_pll1_refclk {
};
&main_usbss0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbss0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb0 {
dr_mode = "host";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wiz2_pll1_refclk {
};
&main_usbss1_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbss1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb1 {
dr_mode = "host";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_cpsw {
};
&main_mmc1_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_i2c0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_i2c1 {
};
&mcu_i2c0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_fss0_ospi0_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&fss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&ospi0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
flash@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
partition@3fc0000 {
label = "ospi.phypattern";
reg = <0x3fc0000 0x40000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
};
&wkup_i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cbass_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_navss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cbass_mcu_wakeup {
- u-boot,dm-spl;
+ bootph-pre-ram;
timer1: timer@40400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <250000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
chipid@43000014 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&mcu_navss {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_ringacc {
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_udmap {
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&secure_proxy_main {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sms {
- u-boot,dm-spl;
+ bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&main_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_uart8_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_mmc1_pins_default {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_pmx0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_pds {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_clks {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&k3_reset {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_uart8 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mcu_cpsw {
};
&main_sdhci0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&main_sdhci1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#address-cells = <2>;
#size-cells = <2>;
- u-boot,dm-spl;
+ bootph-pre-ram;
memorycontroller0: memorycontroller@2990000 {
compatible = "ti,j721s2-ddrss";
ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
instance = <0>;
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,ctl-data = <
DDRSS0_CTL_00_DATA
ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
instance = <1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
ti,ctl-data = <
DDRSS1_CTL_00_DATA
fs_loader0: fs_loader@0 {
compatible = "u-boot,fs-loader";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
a72_0: a72@0 {
ti,sci = <&sms>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
clk_200mhz: dummy_clock_200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
clk_19_2mhz: dummy_clock_19_2mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&cbass_mcu_wakeup {
sa3_secproxy: secproxy@44880000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "ti,am654-secure-proxy";
reg = <0x0 0x44880000 0x0 0x20000>,
<0x0 0x44860000 0x0 0x20000>,
<0x0 0x2a480000 0x0 0x80000>;
reg-names = "rt", "scfg", "target_data";
#mbox-cells = <1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
mbox-names = "tx", "rx", "boot_notify";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
dm_tifs: dm-tifs {
mbox-names = "rx", "tx";
mboxes= <&mcu_secproxy 21>,
<&mcu_secproxy 23>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&wkup_pmx0 {
mcu_uart0_pins_default: mcu-uart0-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */
J721S2_WKUP_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */
};
wkup_uart0_pins_default: wkup-uart0-pins-default {
- u-boot,dm-spl;
+ bootph-pre-ram;
pinctrl-single,pins = <
J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
J721S2_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
mbox-names = "tx", "rx", "notify";
ti,host-id = <4>;
ti,secure-host;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wkup_uart0 {
/{
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
aliases {
usb0 = &usb;
};
&i2c1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usb_phy {
/{
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
aliases {
usb0 = &usb0;
};
&i2c0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&i2c1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usb0_phy {
/{
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&i2c0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&i2c1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/{
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&i2c0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&i2c1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/{
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&i2c1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usb_phy {
* Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
*/
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&gpio1 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio2 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio3 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio4 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio5 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio6 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&i2c1 {
clock-frequency = <400000>;
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&i2c2 {
clock-frequency = <400000>;
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
/delete-node/ &bandgap;
};
&gpio1 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio2 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio3 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio4 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio5 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio6 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&i2c1 {
clock-frequency = <400000>;
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&i2c2 {
clock-frequency = <400000>;
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
/delete-node/ &bandgap;
};
&gpio1 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio2 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio3 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio4 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio5 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio6 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&i2c1 {
clock-frequency = <400000>;
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&i2c2 {
clock-frequency = <400000>;
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
/delete-node/ &bandgap;
&i2c1 {
clock-frequency = <400000>;
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&i2c2 {
};
&gpio1 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio2 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio3 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio4 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio5 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
&gpio6 {
- /delete-property/ u-boot,dm-spl;
+ /delete-property/ bootph-pre-ram;
};
/delete-node/ &bandgap;
*/
&{/soc} {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
+ bootph-pre-ram;
+ bootph-all;
};
&crypto {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sec_jr3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
<0x0 0xff63c000 0x0 0x1000>,
<0x0 0xff638000 0x0 0x400>;
reg-names = "vpu", "hhi", "dmc";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&hdmi_tx {
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
<0x0 0xc883c000 0x0 0x1000>,
<0x0 0xc8838000 0x0 0x1000>;
reg-names = "vpu", "hhi", "dmc";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&hdmi_tx {
spi-flash@0{
compatible = "jedec,spi-nor";
reg = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
spi-flash@0{
compatible = "jedec,spi-nor";
reg = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
*/
&topckgen {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pericfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&apmixedsys {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&timer0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&snfi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
*/
&topckgen {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&topckgen {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pericfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&timer0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&apmixedsys {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
*/
&infracfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pericfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&timer0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mcucfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&dramc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&apmixedsys {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&topckgen {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&snfi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
state_default: pinmux_conf {
- u-boot,dm-pre-reloc;
+ bootph-all;
mux {
function = "jtag";
groups = "ephy_leds_jtag";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
spi-flash@0{
compatible = "jedec,spi-nor";
reg = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
hwver: hwver {
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gpt_clk>;
clock-names = "gpt-clk";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
watchdog: watchdog@1001c000 {
compatible = "mediatek,mt7981-fixed-plls";
reg = <0x1001e000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
topckgen: topckgen@1001b000 {
reg = <0x1001b000 0x1000>;
clock-parent = <&fixed_plls>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
infracfg_ao: infracfg_ao@10001000 {
reg = <0x10001000 0x80>;
clock-parent = <&infracfg>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
infracfg: infracfg@10001000 {
reg = <0x10001000 0x30>;
clock-parent = <&topckgen>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pinctrl: pinctrl@11d00000 {
<&infracfg CK_INFRA_UART>;
mediatek,force-highspeed;
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
uart1: serial@11003000 {
*/
&topckgen {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pericfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&apmixedsys {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&timer0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&snand {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
clock-frequency = <12000000>;
#clock-cells = <0>;
/* must need this line, or uart uanable to get dummy_clk */
- u-boot,dm-pre-reloc;
+ bootph-all;
};
hwver: hwver {
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CK_INFRA_CK_F26M>;
clock-names = "gpt-clk";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
watchdog: watchdog@1001c000 {
<&infracfg CK_INFRA_PWM>;
clock-names = "top", "main", "pwm1", "pwm2";
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
uart0: serial@11002000 {
<&infracfg CK_INFRA_UART>;
mediatek,force-highspeed;
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
uart1: serial@11003000 {
*/
&infracfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&topckgen_ {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&topckgen_cg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&apmixedsys {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
internal-regs {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#ifdef CONFIG_ARMADA_375
/* Armada 375 has multiple timers, use timer1 here */
&timer1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#else
&timer {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#endif
#ifdef CONFIG_SPL_SPI
&spi0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#endif
/{
ocp@68000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
bandgap@48002524 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
reg-shift = <2>;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
reg-shift = <2>;
};
&uart3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
reg-shift = <2>;
};
&mmc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&l4_core {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&scm {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&scm_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
clock-frequency = <100000>;
};
};
ocp {
- u-boot,dm-spl;
+ bootph-pre-ram;
ocp2scp@4a080000 {
compatible = "ti,omap-ocp2scp", "simple-bus";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
ocp2scp@4a090000 {
};
bandgap@4a0021e0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&uart1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
reg-shift = <2>;
};
&uart3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
reg-shift = <2>;
};
&mmc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&mmc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&l4_cfg {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&scm {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&scm_conf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&qspi {
- u-boot,dm-spl;
+ bootph-pre-ram;
m25p80@0 {
compatible = "jedec,spi-nor";
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio6 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio7 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#else /* OMAP54XX */
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&pinctrl_uart3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl_wdog {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio5 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usdhc3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&wdog1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&emmc_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&emmc_cmd {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&emmc_bus8 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
/*
* The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module
* the SPL has been booted from SD Card.
*/
bios-disable-override-hog {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pcfg_pull_none_8ma {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pcfg_pull_up_8ma {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc_bus4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc_cmd {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc_det {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
clock-frequency = <24000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
dmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "rockchip,px30-dmc", "syscon";
reg = <0x0 0xff2a0000 0x0 0x1000>;
};
&uart2 {
clock-frequency = <24000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart5 {
clock-frequency = <24000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&emmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pmugrf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&xin24m {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;
};
&pmucru {
- u-boot,dm-pre-reloc;
+ bootph-all;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-rates;
};
&saradc {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&gpio0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
reg = <0x1800000 0x60000>;
#clock-cells = <1>;
#reset-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
rng: rng@22000 {
reg = <0x1800000 0x60000>;
#clock-cells = <1>;
#reset-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
soc_gpios: pinctrl@1000000 {
gpio-count = <100>;
gpio-bank-name="soc";
#gpio-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
blsp1_uart1: serial@78af000 {
clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
bit-rate = <0xFF>;
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
blsp1_spi1: spi@78b5000 {
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
mdio: mdio@90000 {
/ {
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_north@1300000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
clock-controller@1800000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
serial@78b1000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
leds {
};
&ostm0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&scif2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
clock = <66666666>; /* ToDo: Replace by DM clock driver */
};
&scif2_pins {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usbhs0 {
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/delete-node/ &audma0;
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/delete-node/ &audma0;
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/delete-node/ &audma0;
#include "r8a7790-u-boot.dtsi"
&scif0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
#include "r8a7790-u-boot.dtsi"
&scifa0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
#include "r8a779x-u-boot.dtsi"
&usb_extal_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pfc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rst {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#include "r8a7791-u-boot.dtsi"
&scif0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
#include "r8a7791-u-boot.dtsi"
&scif0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&i2c6 {
#include "r8a779x-u-boot.dtsi"
&usb_extal_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pfc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rst {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&scif0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#include "r8a779x-u-boot.dtsi"
&pfc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rst {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#include "r8a7793-u-boot.dtsi"
&scif0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
#include "r8a779x-u-boot.dtsi"
&usb_extal_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pfc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rst {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&scif2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
#include "r8a7794-u-boot.dtsi"
&scif2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
#include "r8a779x-u-boot.dtsi"
&usb_extal_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pfc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rst {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
sysinfo {
compatible = "renesas,rcar-sysinfo";
i2c-eeprom = <&sysinfo_eeprom>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&i2c_dvfs {
- u-boot,dm-pre-reloc;
+ bootph-all;
sysinfo_eeprom: eeprom@50 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
sysinfo {
compatible = "renesas,rcar-sysinfo";
i2c-eeprom = <&sysinfo_eeprom>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&i2c_dvfs {
- u-boot,dm-pre-reloc;
+ bootph-all;
sysinfo_eeprom: eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
sysinfo {
compatible = "renesas,rcar-sysinfo";
i2c-eeprom = <&sysinfo_eeprom>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&i2c_dvfs {
- u-boot,dm-pre-reloc;
+ bootph-all;
sysinfo_eeprom: eeprom@50 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
sysinfo {
compatible = "renesas,rcar-sysinfo";
i2c-eeprom = <&sysinfo_eeprom>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&i2c_dvfs {
- u-boot,dm-pre-reloc;
+ bootph-all;
sysinfo_eeprom: eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
sysinfo {
compatible = "renesas,rcar-sysinfo";
i2c-eeprom = <&sysinfo_eeprom>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&i2c_dvfs {
- u-boot,dm-pre-reloc;
+ bootph-all;
sysinfo_eeprom: eeprom@50 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
sysinfo {
compatible = "renesas,rcar-sysinfo";
i2c-eeprom = <&sysinfo_eeprom>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&i2c_dvfs {
- u-boot,dm-pre-reloc;
+ bootph-all;
sysinfo_eeprom: eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
#include "r8a779x-u-boot.dtsi"
&extalr_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
sysinfo {
compatible = "renesas,rcar-sysinfo";
i2c-eeprom = <&sysinfo_eeprom>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "renesas,iic-r8a77990",
"renesas,rcar-gen3-iic",
"renesas,rmobile-iic";
- u-boot,dm-pre-reloc;
+ bootph-all;
sysinfo_eeprom: eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
};
&extalr_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&cpg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&extal_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&prr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#include "rk3036-u-boot.dtsi"
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&dmc {
&mmc0 {
fifo-mode;
max-frequency = <4000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
u-boot,spl-fifo-mode;
};
&timer2 {
clock-frequency = <24000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#include "rk3128-u-boot.dtsi"
&emmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
dmc: dmc@20004000 {
compatible = "rockchip,rk3128-dmc", "syscon";
reg = <0x0 0x20004000 0x0 0x1000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
config {
u-boot,boot-led = "rock:red:power";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&cru {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&dmc {
};
&pinctrl {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&timer3 {
compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
clock-frequency = <24000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&emmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
rockchip,grf = <&grf>;
rockchip,msch = <&service_msch>;
rockchip,sram = <&ddr_sram>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
service_msch: syscon@31090000 {
compatible = "rockchip,rk3228-msch", "syscon";
reg = <0x31090000 0x2000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&emmc {
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc {
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&emmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio8 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc_bus4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_clk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_cmd {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_pwr {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/ {
config {
- u-boot,dm-pre-reloc;
+ bootph-all;
u-boot,boot-led = "firefly:green:power";
};
leds {
- u-boot,dm-pre-reloc;
+ bootph-all;
work {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
power {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&emmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio8 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pcfg_pull_up_drv_12ma {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_bus4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_clk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_cmd {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_pwr {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "rk3288-u-boot.dtsi"
/ {
leds {
- u-boot,dm-pre-reloc;
+ bootph-all;
work {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&emmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc_bus4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_clk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_cmd {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_pwr {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&emmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&i2c0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
rk818: pmic@1c {
- u-boot,dm-pre-reloc;
+ bootph-all;
regulators {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&emmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio8 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc_bus4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_clk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_cmd {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_pwr {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&emmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&gpio7 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&emmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&emmc_clk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&emmc_cmd {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&emmc_pwr {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&emmc_bus8 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
#include "rk3288-u-boot.dtsi"
&dmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2_xfer {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio7 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&vcc_sd {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pcfg_pull_none_drv_8ma {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pcfg_pull_up_drv_8ma {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pcfg_pull_none {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pcfg_pull_up {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_bus4 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_cd {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_clk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_cmd {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc_pwr {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
rockchip,pmu = <&pmu>;
rockchip,sgrf = <&sgrf>;
rockchip,sram = <&ddr_sram>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
noc: syscon@ffac0000 {
compatible = "rockchip,rk3288-noc", "syscon";
reg = <0xffac0000 0x2000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio7 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pmu {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sgrf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
};
&vopb {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&vopl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&emmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&gpio3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio7 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio8 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&i2c0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rk808 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&spi2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&spi_flash {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&emmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
clock-frequency = <24000000>;
status = "okay";
};
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
clock-frequency = <24000000>;
status = "okay";
};
};
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&dmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&emmc {
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&saradc {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
dmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "rockchip,px30-dmc", "syscon";
reg = <0x0 0xff2a0000 0x0 0x1000>;
};
/* U-Boot clk driver for px30 cannot set GPU_CLK */
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
assigned-clocks = <&cru PLL_NPLL>,
<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
};
&gpio0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pmucru {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pmugrf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&saradc {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&sfc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&{/spi@ff3a0000/flash@0} {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
clock-frequency = <24000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
clock-frequency = <24000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&xin24m {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc0m1_pin {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pcfg_pull_up_4ma {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
/* Need this and all the pinctrl/gpio stuff above to set pinmux */
&vcc_sd {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gmac2io {
};
&gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc0m1_pin {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pcfg_pull_up_4ma {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb_host0_xhci {
/* Need this and all the pinctrl/gpio stuff above to set pinmux */
&vcc_sd {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc0m1_pin {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pcfg_pull_up_4ma {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb_host0_xhci {
/* Need this and all the pinctrl/gpio stuff above to set pinmux */
&vcc_sd {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pinctrl {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc0m1_pin {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pcfg_pull_up_4ma {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb_host0_xhci {
/* Need this and all the pinctrl/gpio stuff above to set pinmux */
&vcc_sd {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&spi0 {
spi_flash: spiflash@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
dmc: dmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "rockchip,rk3328-dmc";
reg = <0x0 0xff400000 0x0 0x1000
0x0 0xff780000 0x0 0x3000
};
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
clock-frequency = <24000000>;
};
&emmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
u-boot,spl-fifo-mode;
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
u-boot,spl-fifo-mode;
};
&spi0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#include "rk3368-u-boot.dtsi"
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&service_msch {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&dmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&pmugrf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&gpio2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&service_msch {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&dmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
/*
* Validation of throughput using SPEC2000 shows the following
};
&pmugrf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sgrf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&emmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&spi1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
spiflash: w25q32dw@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&timer0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
clock-frequency = <24000000>;
status = "okay";
};
};
&dmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
/*
* PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&service_msch {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&dmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&pmugrf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sgrf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&emmc {
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&timer0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
clock-frequency = <24000000>;
status = "okay";
};
#include "rk3368-u-boot.dtsi"
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&service_msch {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&dmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&pmugrf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&i2c0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rk808 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&tcphy1 {
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
};
&spi_flash {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdhci {
max-frequency = <25000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc {
max-frequency = <20000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&spiflash {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&vdd_log {
&sdhci {
max-frequency = <25000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc {
max-frequency = <20000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&gpio1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpio3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
/*
* The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
* eMMC and SPI after the SPL has been booted from SD Card.
*/
bios_disable_override {
- u-boot,dm-pre-reloc;
+ bootph-all;
gpios = <RK_PD5 GPIO_ACTIVE_LOW>;
output-high;
line-name = "bios_disable_override";
};
&gpio4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&norflash {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pcfg_pull_none {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pcfg_pull_up {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc_bus4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc_cmd {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&spi1 {
spi_flash: flash@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&spi1 {
spi_flash: flash@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
cic: syscon@ff620000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "rockchip,rk3399-cic", "syscon";
reg = <0x0 0xff620000 0x0 0x100>;
};
dfi: dfi@ff630000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x00 0xff630000 0x00 0x4000>;
compatible = "rockchip,rk3399-dfi";
rockchip,pmu = <&pmugrf>;
};
dmc: dmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "rockchip,rk3399-dmc";
devfreq-events = <&dfi>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
};
pmusgrf: syscon@ff330000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "rockchip,rk3399-pmusgrf", "syscon";
reg = <0x0 0xff330000 0x0 0xe3d4>;
};
#endif /* CONFIG_ROCKCHIP_SPI_IMAGE && CONFIG_HAS_ROM */
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&emmc_phy {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pmu {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pmugrf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pmu {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pmucru {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdhci {
max-frequency = <200000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
};
&spi1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&vopb {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&vopl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
clock-frequency = <24000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
};
dmc: dmc {
compatible = "rockchip,rk3568-dmc";
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&cru {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&pmucru {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&pmugrf {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&sdhci {
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
};
&sdmmc0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
};
noc: syscon@10128000 {
compatible = "rockchip,rk3188-noc", "syscon";
reg = <0x10128000 0x2000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
dmc: dmc@20020000 {
rockchip,grf = <&grf>;
rockchip,pmu = <&pmu>;
rockchip,noc = <&noc>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pmu {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
#include "rockchip-u-boot.dtsi"
&grf {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
dmc {
compatible = "rockchip,rv1126-dmc";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&gpio0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&gpio1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&grf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pmu {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pmugrf {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&xin24m {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&cru {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&pmucru {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&emmc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&cpg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&ehci0 {
};
&extal_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&extalr_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pfc {
};
&prr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rpc {
compatible = "nexell,nexell-display";
reg = <0xc0102800 0x100>;
index = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "disabled";
};
pinctrl@C0010000 {
compatible = "nexell,s5pxx18-pinctrl";
reg = <0xc0010000 0xf000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
uart0:uart@c00a1000 {
/{
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
gmac: ethernet@e0220000 {
compatible = "actions,s700-ethernet";
};
&uart3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&cmu {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/{
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&uart5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&cmu {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ahb {
- u-boot,dm-pre-reloc;
+ bootph-all;
apb {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
};
&clk32 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&dbgu {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&main_rc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&main_xtal {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_dbgu {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pioA {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pioB {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&slow_xtal {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&slow_rc_osc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
usb1: ohci@400000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
hlcdc: hlcdc@f0000000 {
compatible = "atmel,at91sam9x5-hlcdc";
reg = <0xf0014000 0x160>;
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
main: mainck {
compatible = "atmel,at91sam9x5-clk-main";
#clock-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
plla: pllack@0 {
atmel,clk-input-range = <12000000 12000000>;
#atmel,pll-clk-output-range-cells = <4>;
atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
plladiv: plladivck {
#clock-cells = <0>;
clocks = <&main>;
regmap-sfr = <&sfr>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
mck: masterck {
clocks = <&main>, <&plladiv>, <&utmi>;
atmel,clk-output-range = <124000000 166000000>;
atmel,clk-divisors = <1 2 4 3>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
h32ck: h32mxck {
#clock-cells = <0>;
compatible = "atmel,sama5d4-clk-h32mx";
clocks = <&mck>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
usb: usbck {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&h32ck>;
- u-boot,dm-pre-reloc;
+ bootph-all;
macb0_clk: macb0_clk@5 {
#clock-cells = <0>;
#clock-cells = <0>;
reg = <18>;
atmel,clk-output-range = <0 83000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
flx0_clk: flx0_clk@19 {
#clock-cells = <0>;
reg = <24>;
atmel,clk-output-range = <0 83000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
uart1_clk: uart1_clk@25 {
#clock-cells = <0>;
reg = <25>;
atmel,clk-output-range = <0 83000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
uart2_clk: uart2_clk@26 {
#clock-cells = <0>;
reg = <26>;
atmel,clk-output-range = <0 83000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
uart3_clk: uart3_clk@27 {
#clock-cells = <0>;
reg = <33>;
atmel,clk-output-range = <0 83000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
spi1_clk: spi1_clk@34 {
#clock-cells = <0>;
reg = <35>;
atmel,clk-output-range = <0 83000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
tcb1_clk: tcb1_clk@36 {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
- u-boot,dm-pre-reloc;
+ bootph-all;
dma0_clk: dma0_clk@6 {
#clock-cells = <0>;
sdmmc0_hclk: sdmmc0_hclk@31 {
#clock-cells = <0>;
reg = <31>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
sdmmc1_hclk: sdmmc1_hclk@32 {
#clock-cells = <0>;
reg = <32>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
lcdc_clk: lcdc_clk@45 {
qspi0_clk: qspi0_clk@52 {
#clock-cells = <0>;
reg = <52>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
qspi1_clk: qspi1_clk@53 {
#clock-cells = <0>;
reg = <53>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
#size-cells = <0>;
interrupt-parent = <&pmc>;
clocks = <&main>, <&plla>, <&utmi>, <&mck>;
- u-boot,dm-pre-reloc;
+ bootph-all;
sdmmc0_gclk: sdmmc0_gclk@31 {
#clock-cells = <0>;
reg = <31>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
sdmmc1_gclk: sdmmc1_gclk@32 {
#clock-cells = <0>;
reg = <32>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
tcb0_gclk: tcb0_gclk@35 {
clock-names = "t0_clk", "gclk", "slow_clk";
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
clocks = <&pioA_clk>;
gpio-controller;
#gpio-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_sck_cs_default &pinctrl_qspi1_dat_default>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
spi_flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
pinmux = <PIN_PB5__QSPI1_SCK>,
<PIN_PB6__QSPI1_CS>;
bias-disable;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pinctrl_qspi1_dat_default: qspi1_dat_default {
<PIN_PB9__QSPI1_IO2>,
<PIN_PB10__QSPI1_IO3>;
bias-pull-up;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
mmc0: mmc@f0000000 {
compatible = "atmel,hsmci";
};
pinctrl@fffff200 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
};
dbgu {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_dbgu: dbgu-0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
};
mmc0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
};
pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
};
pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
};
mmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
};
pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
};
spi0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_spi0: spi0-0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
};
spi1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_spi1: spi1-0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioB: gpio@fffff400 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioC: gpio@fffff600 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioD: gpio@fffff800 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioD_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioE: gpio@fffffa00 {
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioE_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pmc: pmc@fffffc00 {
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
main_rc_osc: main_rc_osc {
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
interrupts = <AT91_PMC_LOCKU>;
clocks = <&main>;
regmap-sfr = <&sfr>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
mck: masterck {
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
atmel,clk-output-range = <0 166000000>;
atmel,clk-divisors = <1 2 4 3>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
usb: usbck {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mck>;
- u-boot,dm-pre-reloc;
+ bootph-all;
dbgu_clk: dbgu_clk@2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <2>;
};
};
pioA_clk: pioA_clk@6 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <6>;
};
pioB_clk: pioB_clk@7 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <7>;
};
pioC_clk: pioC_clk@8 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <8>;
};
pioD_clk: pioD_clk@9 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <9>;
};
pioE_clk: pioE_clk@10 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <10>;
};
};
mci0_clk: mci0_clk@21 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <21>;
};
mci1_clk: mci1_clk@22 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <22>;
};
spi0_clk: spi0_clk@24 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <24>;
atmel,clk-output-range = <0 133000000>;
};
spi1_clk: spi1_clk@25 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <25>;
atmel,clk-output-range = <0 133000000>;
reg = <0xfffffe30 0xf>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
clocks = <&mck>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
watchdog@fffffe40 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb888_alt>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
display-timings {
- u-boot,dm-pre-reloc;
+ bootph-all;
800x480 {
clock-frequency = <24000000>;
hactive = <800>;
vfront-porch = <22>;
vback-porch = <21>;
vsync-len = <5>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &dbgu;
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
slot@0 {
reg = <0>;
bus-width = <4>;
spi0: spi@f0004000 {
dmas = <0>, <0>; /* Do not use DMA for spi0 */
- u-boot,dm-pre-reloc;
+ bootph-all;
spi_flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
slot@0 {
reg = <0>;
bus-width = <4>;
pinctrl@fffff200 {
board {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_mmc0_cd: mmc0_cd {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD17 GPIO with pullup deglitch */
};
pinctrl_mmc1_cd: mmc1_cd {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD18 GPIO with pullup deglitch */
};
dbgu: serial@ffffee00 {
dmas = <0>, <0>; /* Do not use DMA for dbgu */
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
watchdog@fffffe40 {
compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
stdout-path = &dbgu;
};
dbgu: serial@ffffee00 {
dmas = <0>, <0>; /* Do not use DMA for dbgu */
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
watchdog@fffffe40 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
usb0: gadget@00400000 {
#address-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
- u-boot,dm-pre-reloc;
+ bootph-all;
hlcdc: hlcdc@f0000000 {
compatible = "atmel,at91sam9x5-hlcdc";
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
main_rc_osc: main_rc_osc {
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
interrupt-parent = <&pmc>;
interrupts = <AT91_PMC_MOSCSELS>;
clocks = <&main_rc_osc &main_osc>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
plla: pllack@0 {
interrupt-parent = <&pmc>;
interrupts = <AT91_PMC_LOCKU>;
clocks = <&main>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
mck: masterck {
#clock-cells = <0>;
compatible = "atmel,sama5d4-clk-h32mx";
clocks = <&mck>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
usb: usbck {
compatible = "atmel,at91rm9200-clk-system";
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ddrck: ddrck@2 {
#clock-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&h32ck>;
- u-boot,dm-pre-reloc;
+ bootph-all;
pioD_clk: pioD_clk@5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <5>;
};
};
pioA_clk: pioA_clk@23 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <23>;
};
pioB_clk: pioB_clk@24 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <24>;
};
pioC_clk: pioC_clk@25 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <25>;
};
pioE_clk: pioE_clk@26 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <26>;
};
};
usart3_clk: usart3_clk@30 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <30>;
};
};
mci1_clk: mci1_clk@36 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <36>;
};
spi0_clk: spi0_clk@37 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <0>;
reg = <37>;
};
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pioD: gpio@fc068000 {
};
pinctrl@fc06a000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
};
mmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
>;
};
pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
};
spi0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_spi0: spi0-0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
};
usart3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl_usart3: usart3-0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
atmel,pins =
<AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
*/
/{
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&clkmgr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rst {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sysmgr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
memory {
#address-cells = <2>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
ccu: cache-controller@f7000000 {
compatible = "arteris,ncore-ccu";
reg = <0xf7000000 0x100900>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&clkmgr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gmac1 {
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rst {
compatible = "altr,rst-mgr";
altr,modrst-offset = <0x20>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdr {
<0xf8010000 0x190>,
<0xf8011000 0x500>;
resets = <&rst DDRSCH_RESET>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sysmgr {
compatible = "altr,sys-mgr", "syscon";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&watchdog0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
compatible = "jedec,spi-nor";
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&i2c1 {
&mmc {
drvsel = <3>;
smplsel = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
};
&watchdog0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <EOSC1_CLK_HZ>;
clock-output-names = "altera_arria10_hps_eosc1-clk";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
#clock-cells = <0>;
clock-frequency = <CB_INTOSC_LS_CLK_HZ>;
clock-output-names = "altera_arria10_hps_cb_intosc_ls-clk";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* Clock source: altera_arria10_hps_f2h_free */
#clock-cells = <0>;
clock-frequency = <F2H_FREE_CLK_HZ>;
clock-output-names = "altera_arria10_hps_f2h_free-clk";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "altr,socfpga-a10-clk-init";
reg = <0xffd04000 0x00000200>;
reg-names = "soc_clock_manager_OCP_SLV";
- u-boot,dm-pre-reloc;
+ bootph-all;
mainpll {
vco0-psrc = <MAINPLLGRP_VCO0_PSRC>;
nocdiv-csatclk = <MAINPLLGRP_NOCDIV_CSATCLK>;
nocdiv-cstraceclk = <MAINPLLGRP_NOCDIV_CSTRACECLK>;
nocdiv-cspdbgclk = <MAINPLLGRP_NOCDIV_CSPDBGCLK>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
perpll {
emacctl-emac1sel = <PERPLLGRP_EMACCTL_EMAC1SEL>;
emacctl-emac2sel = <PERPLLGRP_EMACCTL_EMAC2SEL>;
gpiodiv-gpiodbclk = <PERPLLGRP_GPIODIV_GPIODBCLK>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
alteragrp {
nocclk = <ALTERAGRP_NOCCLK>;
mpuclk = <ALTERAGRP_MPUCLK>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "pinctrl-single";
reg = <0xffd07000 0x00000800>;
reg-names = "soc_3v_io48_pin_mux_OCP_SLV";
- u-boot,dm-pre-reloc;
+ bootph-all;
shared {
reg = <0xffd07000 0x00000200>;
<0x000000b4 PINMUX_SHARED_IO_Q4_10_SEL>,
<0x000000b8 PINMUX_SHARED_IO_Q4_11_SEL>,
<0x000000bc PINMUX_SHARED_IO_Q4_12_SEL>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
dedicated {
<0x00000038 PINMUX_DEDICATED_IO_15_SEL>,
<0x0000003c PINMUX_DEDICATED_IO_16_SEL>,
<0x00000040 PINMUX_DEDICATED_IO_17_SEL>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
dedicated_cfg {
<0x0000013c CONFIG_IO_MACRO (CONFIG_IO_15)>,
<0x00000140 CONFIG_IO_MACRO (CONFIG_IO_16)>,
<0x00000144 CONFIG_IO_MACRO (CONFIG_IO_17)>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
fpga {
<0x00000038 PINMUX_SPIS1_USEFPGA_SEL>,
<0x0000003c PINMUX_UART0_USEFPGA_SEL>,
<0x00000040 PINMUX_UART1_USEFPGA_SEL>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "altr,socfpga-a10-noc";
reg = <0xffd10000 0x00008000>;
reg-names = "mpu_m0";
- u-boot,dm-pre-reloc;
+ bootph-all;
firewall {
mpu0 = <0x00000000 0x0000ffff>;
fpga2sdram0-0 = <0x00000000 0x0000ffff>;
fpga2sdram1-0 = <0x00000000 0x0000ffff>;
fpga2sdram2-0 = <0x00000000 0x0000ffff>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
hps_fpgabridge0: fpgabridge@0 {
compatible = "altr,socfpga-hps2fpga-bridge";
init-val = <H2F_AXI_MASTER>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
hps_fpgabridge1: fpgabridge@1 {
compatible = "altr,socfpga-lwhps2fpga-bridge";
init-val = <LWH2F_AXI_MASTER>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
hps_fpgabridge2: fpgabridge@2 {
compatible = "altr,socfpga-fpga2hps-bridge";
init-val = <F2H_AXI_SLAVE>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
hps_fpgabridge3: fpgabridge@3 {
compatible = "altr,socfpga-fpga2sdram0-bridge";
init-val = <F2SDRAM0_AXI_SLAVE>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
hps_fpgabridge4: fpgabridge@4 {
compatible = "altr,socfpga-fpga2sdram1-bridge";
init-val = <F2SDRAM1_AXI_SLAVE>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
hps_fpgabridge5: fpgabridge@5 {
compatible = "altr,socfpga-fpga2sdram2-bridge";
init-val = <F2SDRAM2_AXI_SLAVE>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
/ {
chosen {
tick-timer = &timer2;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
memory@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&clkmgr {
- u-boot,dm-pre-reloc;
+ bootph-all;
clocks {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&cb_intosc_hs_div2_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&cb_intosc_ls_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&f2s_free_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gmac0 {
};
&L2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&l4_mp_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&l4_sp_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&l4_sys_free_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&main_periph_ref_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&main_pll {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&main_noc_base_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&noc_free_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&osc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&peri_noc_base_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&periph_pll {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&porta {
};
&rst {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sysmgr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&timer2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
chosen {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
clocks {
- u-boot,dm-pre-reloc;
+ bootph-all;
altera_arria10_hps_eosc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
altera_arria10_hps_cb_intosc_ls {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
altera_arria10_hps_f2h_free {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
clock_manager@0xffd04000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
mainpll {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
perpll {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
alteragrp {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
pinmux@0xffd07000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
shared {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
dedicated {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
dedicated_cfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
fpga {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
noc@0xffd10000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
firewall {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
fpgabridge@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
fpgabridge@1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
fpgabridge@2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
fpgabridge@3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
fpgabridge@4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
fpgabridge@5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
fs_loader0: fs-loader {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "u-boot,fs-loader";
phandlepart = <&mmc 1>;
};
};
&atsha204a {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&fpga_mgr {
- u-boot,dm-pre-reloc;
+ bootph-all;
altr,bitstream = "fpga.itb";
};
&i2c1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&main_sdmmc_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&peri_sdmmc_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc_free_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&watchdog1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
fs_loader0: fs-loader {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "u-boot,fs-loader";
phandlepart = <&mmc 1>;
};
};
&fpga_mgr {
- u-boot,dm-pre-reloc;
+ bootph-all;
altr,bitstream = "fit_spl_fpga.itb";
};
&mmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* Clock available early */
&main_sdmmc_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&peri_sdmmc_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc_free_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
vmmc-supply = <®ulator_3_3v>;
vqmmc-supply = <®ulator_3_3v>;
bus-width = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&nand0 {
&uart0 {
clock-frequency = <100000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&watchdog0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&mmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&flash {
compatible = "n25q00", "jedec,spi-nor";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
clock-frequency = <100000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
&mmc0 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usb1 {
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&watchdog0 {
};
&mmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
clock-frequency = <100000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
&mmc0 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usb1 {
&uart0 {
clock-frequency = <100000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&watchdog0 {
&mmc0 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usb1 {
&uart0 {
clock-frequency = <100000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&watchdog0 {
&mmc0 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usb1 {
&uart0 {
clock-frequency = <100000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&watchdog0 {
&mmc0 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
cd-gpios = <&portb 18 0>;
vmmc-supply = <®ulator_3_3v>;
&qspi {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
flash0: n25q00@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q00", "jedec,spi-nor";
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&watchdog0 {
};
&mmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
clock-frequency = <100000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&porta {
};
&mmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&flash0 {
compatible = "n25q00", "jedec,spi-nor";
- u-boot,dm-pre-reloc;
+ bootph-all;
partition@qspi-boot {
/* 8MB for raw data. */
&uart0 {
clock-frequency = <100000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
};
&mmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&flash {
compatible = "n25q00", "jedec,spi-nor";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
clock-frequency = <100000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
};
&mmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&flash {
compatible = "n25q256a", "jedec,spi-nor";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
clock-frequency = <100000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
&mmc0 {
status = "okay";
bus-width = <8>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usb1 {
&qspi {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
flash0: n25q00@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q00", "jedec,spi-nor";
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
n25q128@0 {
compatible = "n25q128", "jedec,spi-nor";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
n25q00@1 {
compatible = "n25q00", "jedec,spi-nor";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&uart0 {
clock-frequency = <100000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
};
&watchdog0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
memory {
#address-cells = <2>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
ccu: cache-controller@f7000000 {
compatible = "arteris,ncore-ccu";
reg = <0xf7000000 0x100900>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
clocks {
&clkmgr {
compatible = "intel,n5x-clkmgr";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gmac0 {
};
&memclkmgr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&mmc {
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rst {
compatible = "altr,rst-mgr";
altr,modrst-offset = <0x20>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdr {
resets = <&rst DDRSCH_RESET>;
clocks = <&memclkmgr>;
clock-names = "mem_clk";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&spi0 {
&sysmgr {
compatible = "altr,sys-mgr", "syscon";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&timer0 {
&uart0 {
clocks = <&clkmgr N5X_L4_SP_CLK>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
&usb0 {
clocks = <&clkmgr N5X_USB_CLK>;
disable-over-current;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usb1 {
clocks = <&clkmgr N5X_USB_CLK>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&watchdog0 {
clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&watchdog1 {
compatible = "jedec,spi-nor";
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&i2c1 {
&mmc {
drvsel = <3>;
smplsel = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
};
&watchdog0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
device_type = "soc";
interrupt-parent = <&intc>;
ranges = <0 0 0 0xffffffff>;
- u-boot,dm-pre-reloc;
+ bootph-all;
clkmgr: clkmgr@ffd10000 {
compatible = "altr,clk-mgr";
interrupts = <0 96 4>;
fifo-depth = <0x400>;
resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "disabled";
};
compatible = "altr,rst-mgr";
reg = <0xffd11000 0x1000>;
altr,modrst-offset = <0x20>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
sdr: sdr@f8000400 {
<0xf8010000 0x190>,
<0xf8011000 0x500>;
resets = <&rst DDRSCH_RESET>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
spi0: spi@ffda4000 {
reg-io-width = <4>;
resets = <&rst UART0_RESET>;
clock-frequency = <100000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "disabled";
};
};
&clkmgr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&flash0 {
spi-max-frequency = <100000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sysmgr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&watchdog0 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* 4GB */
reg = <0 0x00000000 0 0x80000000>,
<1 0x80000000 0 0x80000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
/
{
framebuffer@9D400000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
serial@a84000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
clock-controller@100000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
gpio_north@3900000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pinctrl_north@3900000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
#include <dt-bindings/memory/stm32-sdram.h>
/{
clocks {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
aliases {
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
pin-controller {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
fmc: fmc@A0000000 {
pinctrl-0 = <&fmc_pins_d32>;
pinctrl-names = "default";
st,mem_remap = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
/*
* Memory configuration from sdram
};
&clk_hse {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clk_lse {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clk_i2s_ckin {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pwrcfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&syscfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rcc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioa {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiob {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiod {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioe {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiof {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiog {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioh {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioj {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiok {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
usart1_pins_a: usart1-0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
fmc_pins_d32: fmc_d32@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins
{
pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
<STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
<STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
slew-rate = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&timers5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
* Memory configuration from sdram datasheet IS42S32800G-6BLI
*/
bank1: bank@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
st,sdram-control = /bits/ 8 <NO_COL_9
NO_ROW_12
MWIDTH_32
};
usart1_pins_a: usart1-0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
#include <dt-bindings/memory/stm32-sdram.h>
/{
clocks {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
aliases {
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
reg = <0xa0000000 0x1000>;
pinctrl-names = "default";
st,syscfg = <&syscfg>;
st,swp_fmc = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
/*
* Memory configuration from sdram datasheet
};
&clk_hse {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clk_i2s_ckin {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clk_lse {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioa {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiob {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiod {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioe {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiof {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiog {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioh {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioj {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiok {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
usart1_pins_a: usart1-0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
fmc_pins: fmc@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins
{
pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
<STM32_PINMUX('B', 5, AF12)>, /* SDCKE1 */
<STM32_PINMUX('G', 8, AF12)>; /* SDCLK */
slew-rate = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&pwrcfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rcc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&timers5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#include <dt-bindings/memory/stm32-sdram.h>
/{
clocks {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
aliases {
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
pinctrl-0 = <&fmc_pins_d32>;
pinctrl-names = "default";
st,mem_remap = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
/*
* Memory configuration from sdram
};
&clk_hse {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clk_i2s_ckin {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clk_lse {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioa {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiob {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiod {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioe {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiof {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiog {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioh {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioj {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiok {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
fmc_pins_d32: fmc_d32@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins
{
pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
<STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
<STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
slew-rate = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
usart3_pins_a: usart3-0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&pwrcfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
};
&rcc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&syscfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&timers5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
#include <dt-bindings/memory/stm32-sdram.h>
/{
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
fmc: fmc@A0000000 {
compatible = "st,stm32-fmc";
pinctrl-0 = <&fmc_pins>;
pinctrl-names = "default";
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
mac: ethernet@40028000 {
};
&clk_hse {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioa {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiob {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiod {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioe {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiof {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiog {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioh {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
fmc_pins: fmc@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins
{
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&pwrcfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rcc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&timers5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&usart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
};
pinctrl-0 = <<dc_pins>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&fmc {
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
bank1: bank@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
st,sdram-control = /bits/ 8 <NO_COL_8
NO_ROW_12
MWIDTH_16
};
usart1_pins_b: usart1-1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&pwrcfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&qspi {
<&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
<&clk_hse>;
clock-names = "pclk", "px_clk", "ref";
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
ports {
clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
ports {
port@0 {
&fmc {
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
bank1: bank@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
st,sdram-control = /bits/ 8 <NO_COL_8
NO_ROW_12
MWIDTH_32
};
usart1_pins_a: usart1-0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
/{
clocks {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
aliases {
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
pin-controller {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
fmc: fmc@52004000 {
};
&clk_hse {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clk_i2s {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clk_lse {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&fmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioa {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,stm32-gpio";
};
&gpiob {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,stm32-gpio";
};
&gpioc {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,stm32-gpio";
};
&gpiod {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,stm32-gpio";
};
&gpioe {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,stm32-gpio";
};
&gpiof {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,stm32-gpio";
};
&gpiog {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,stm32-gpio";
};
&gpioh {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,stm32-gpio";
};
&gpioi {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,stm32-gpio";
};
&gpioj {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,stm32-gpio";
};
&gpiok {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,stm32-gpio";
};
&pwrcfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rcc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc1 {
};
&timer5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
firmware {
optee {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
/* need PSCI for sysreset during board_f */
psci {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
ddr: ddr@5a003000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,stm32mp13-ddr";
};
&bsec {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioa {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiob {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiod {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioe {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiof {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiog {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioh {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&iwdg2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rcc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&scmi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&scmi_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&scmi_reset {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&scmi_shm {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&scmi_sram {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&syscfg {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
"ddrphycapb";
config-DDR_MEM_COMPATIBLE {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = __stringify(st,DDR_MEM_COMPATIBLE);
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
ddr: ddr@5a003000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,stm32mp1-ddr";
/* need PSCI for sysreset during board_f */
psci {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
};
&bsec {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioa {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiob {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiod {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioe {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiof {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiog {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioh {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioj {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiok {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioz {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&optee {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&iwdg2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* pre-reloc probe = reserve video frame buffer in video_reserve() */
<dc {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
/* temp = waiting kernel update */
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_z {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rcc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&scmi {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
&usart1 {
};
clocks {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* need PSCI for sysreset during board_f */
psci {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
reboot {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "syscon-reboot";
regmap = <&rcc>;
offset = <0x404>;
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
ddr: ddr@5a003000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,stm32mp1-ddr";
};
&bsec {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clk_csi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clk_hsi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clk_hse {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clk_lsi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clk_lse {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&cpu0_opp_table {
- u-boot,dm-spl;
+ bootph-pre-ram;
opp-650000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
opp-800000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&gpioa {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiob {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiod {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioe {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiof {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiog {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioh {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioj {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpiok {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gpioz {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&iwdg2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* pre-reloc probe = reserve video frame buffer in video_reserve() */
<dc {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
/* temp = waiting kernel update */
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_z {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pwr_regulators {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rcc {
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <0>;
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
/* pull-up on rx to avoid floating level */
bias-pull-up;
};
};
reserved-memory {
- u-boot,dm-spl;
+ bootph-pre-ram;
optee@de000000 {
reg = <0xde000000 0x02000000>;
no-map;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
#endif
};
&i2c4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&i2c4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&pmic {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rcc {
reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&sdmmc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc1_b4_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
/* pull-up on rx to avoid floating level */
bias-pull-up;
};
};
&sdmmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc1_b4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
bias-pull-up;
};
};
};
&sdmmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc1_b4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
bias-pull-up;
};
};
#include "stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi"
&vddcore {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&vdd {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&vdd_usb {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&vdda {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&vdd_ddr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&vtt_ddr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&vref_ddr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&vdd_sd {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&v3v3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&v2v8 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&v1v8 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rcc {
reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&sdmmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc1_b4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
bias-pull-up;
};
};
};
&sdmmc1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdmmc1_b4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
bias-pull-up;
};
};
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
&vin {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&vddcore {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&vdd {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&vddq_ddr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rcc {
reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
/* pull-up on rx to avoid floating level */
bias-pull-up;
};
};
&i2c4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&i2c4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&pmic {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rcc {
reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&sdmmc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc1_b4_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc1_dir_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc2_b4_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc2_d47_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
/* pull-up on rx to avoid floating level */
bias-pull-up;
};
};
&flash0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&qspi {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&qspi_clk_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&qspi_bk1_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&qspi_bk2_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&i2c2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&i2c2_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&pmic {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rcc {
reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&sdmmc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc2_b4_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc2_d47_pins_d {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&sdmmc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc1_b4_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&i2c4 {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
+ bootph-all;
+ bootph-pre-ram;
eeprom0: eeprom@50 {
};
};
&i2c4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&pmic {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
+ bootph-all;
+ bootph-pre-ram;
regulators {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&flash0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&qspi {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&qspi_clk_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&qspi_bk1_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&qspi_bk2_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* VCO = 600.0 MHz => P = 100, Q = 50, R = 50 */
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 1 49 5 11 11 PQR(1,1,1) >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&sdmmc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
st,use-ckin;
st,cmd-gpios = <&gpiod 2 0>;
st,ck-gpios = <&gpioc 12 0>;
};
&sdmmc1_b4_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc1_dir_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc2_b4_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc2_d47_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
/* pull-up on rx to avoid floating level */
bias-pull-up;
};
};
®11 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
®18 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb33 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbotg_hs_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbotg_hs {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbphyc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbphyc_port0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbphyc_port1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&vdd_usb {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
st,use-ckin;
st,cmd-gpios = <&gpiod 2 0>;
st,ck-gpios = <&gpioc 12 0>;
};
&sdmmc1_b4_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc1_dir_pins_b {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc2_b4_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc2_d47_pins_c {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4_pins_b {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
/delete-property/ bias-disable;
bias-pull-up;
};
};
&vdd_io {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
st,use-ckin;
st,cmd-gpios = <&gpiod 2 0>;
st,ck-gpios = <&gpioc 12 0>;
};
&sdmmc1_b4_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc1_dir_pins_b {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc2_b4_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc2_d47_pins_c {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4_pins_d {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
/delete-property/ bias-disable;
bias-pull-up;
};
};
&sdmmc1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
st,use-ckin;
st,cmd-gpios = <&gpiod 2 0>;
st,ck-gpios = <&gpioc 12 0>;
};
&sdmmc1_b4_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc1_dir_pins_b {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&sdmmc2_b4_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&sdmmc2_d47_pins_c {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&uart4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart4_pins_b {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pins2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
/delete-property/ bias-disable;
bias-pull-up;
};
#include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
/ {
- u-boot,dm-pre-reloc;
+ bootph-all;
aliases {
eeprom0 = &eeprom0;
};
&flash0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c4 {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
+ bootph-all;
+ bootph-pre-ram;
eeprom0: eeprom@53 {
};
};
&i2c4_pins_a {
- u-boot,dm-pre-reloc;
+ bootph-all;
pins {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&pmic {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
+ bootph-all;
+ bootph-pre-ram;
regulators {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&pwr_regulators {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&qspi {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&qspi_clk_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&qspi_bk1_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
pins1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
pins2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 99 */
compatible = "st,stm32mp1-pll";
reg = <3>;
cfg = < 3 98 5 7 5 PQR(1,1,1) >;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
®11 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
®18 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usb33 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbotg_hs_pins_a {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbotg_hs {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbphyc {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbphyc_port0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&usbphyc_port1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&vdd_usb {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
// SPDX-License-Identifier: GPL-2.0+ OR MIT
&serial0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pmgr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&ps_sio_busif {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&ps_sio {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&ps_uart_p {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&ps_uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
host1x@50000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
dc@54200000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
/ {
host1x@50000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
dc@54200000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
/ {
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
timer@60000200 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
serial@54006800 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
serial@54006900 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
serial@54006a00 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
soc-glue@5f800000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
emmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
};
&emmc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
dcc: dcc {
compatible = "arm,dcc";
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
amba: amba {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
#address-cells = <0x2>;
#size-cells = <0x2>;
dcc: dcc {
compatible = "arm,dcc";
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
amba: amba {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
#address-cells = <0x2>;
#size-cells = <0x2>;
dcc: dcc {
compatible = "arm,dcc";
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
amba: amba {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
#address-cells = <0x2>;
#size-cells = <0x2>;
dcc: dcc {
compatible = "arm,dcc";
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
amba: amba {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
#address-cells = <0x2>;
#size-cells = <0x2>;
dcc: dcc {
compatible = "arm,dcc";
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
clk1: clk1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
dcc: dcc {
compatible = "arm,dcc";
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
amba: axi {
compatible = "simple-bus";
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <2>;
#size-cells = <2>;
ranges;
serial0: serial@f1920000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "arm,pl011", "arm,primecell";
reg = <0 0xf1920000 0 0x1000>;
reg-io-width = <4>;
/ {
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&aips0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_ddr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
/ {
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&aips0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&dcu0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&iomuxc {
};
&pinctrl_ddr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl_uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
amba: axi {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
slcr: slcr@f8000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
reg = <0xF8000000 0x1000>;
ranges;
clkc: clkc@100 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
};
scutimer: timer@f8f00600 {
- u-boot,dm-pre-reloc;
+ bootph-all;
interrupt-parent = <&intc>;
interrupts = <1 13 0x301>;
compatible = "arm,cortex-a9-twd-timer";
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
amba: amba {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
slcr: slcr@f8000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
reg = <0xF8000000 0x1000>;
ranges;
clkc: clkc@100 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
clock-output-names = "armpll", "ddrpll",
};
scutimer: timer@f8f00600 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clock-frequency = <333333333>;
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
amba: amba {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
slcr: slcr@f8000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
reg = <0xF8000000 0x1000>;
ranges;
clkc: clkc@100 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
clock-output-names = "armpll", "ddrpll",
* why place cfi-flash directly here.
*/
flash@e2000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "cfi-flash";
reg = <0xe2000000 0x2000000>;
#address-cells = <1>;
};
scutimer: timer@f8f00600 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clock-frequency = <333333333>;
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
amba: amba {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
slcr: slcr@f8000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
fclk-enable = <0xf>;
- u-boot,dm-pre-reloc;
+ bootph-all;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
};
scutimer: timer@f8f00600 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clock-frequency = <333333333>;
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
is-dual = <0>;
num-cs = <1>;
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay"; /* EMMC MTFC4GACAJCN - MIO40-MIO45 */
non-removable;
bus-width = <4>;
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay"; /* MIO8/9 */
};
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&sdhci1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
is-dual = <0>;
num-cs = <1>;
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
num-cs = <1>;
flash@0 {
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
num-cs = <1>;
flash@0 {
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
num-cs = <1>;
flash@0 {
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&sdhci0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
&i2c0 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
clock-frequency = <400000>;
i2c-mux@74 { /* this cover MGT board */
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
- u-boot,dm-pre-reloc;
+ bootph-all;
/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
i2c@0 {
#address-cells = <1>;
/* Use for storing information about SC board */
eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */
compatible = "atmel,24c32";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x50>;
};
};
&i2c1 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
clock-frequency = <400000>;
i2c-mux@74 { /* This cover processor board */
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
- u-boot,dm-pre-reloc;
+ bootph-all;
/* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
i2c@0 {
#address-cells = <1>;
/* Use for storing information about SC board */
eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */
compatible = "atmel,24c32";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x50>;
};
};
};
pss_ref_clk: pss_ref_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33333333>;
};
video_clk: video_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
pss_alt_ref_clk: pss_alt_ref_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
gt_crx_ref_clk: gt_crx_ref_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <108000000>;
};
aux_ref_clk: aux_ref_clk {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
&zynqmp_firmware {
zynqmp_clk: clock-controller {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
&uart0 { /* uart0 MIO38-39 */
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gem0 {
status = "okay";
is-decoded-cs = <0>;
num-cs = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
displayspi@0 {
compatible = "syncoam,seps525";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0>;
status = "okay";
spi-max-frequency = <10000000>;
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
clk_xin: clk_xin {
ranges;
sdhci0: sdhci@ff160000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
non-removable;
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
clk_xin: clk_xin {
ranges;
sdhci1: sdhci@ff170000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
non-removable;
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
amba: amba {
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
amba: amba {
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
amba {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
uart1: serial@ff010000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
reg = <0xff010000 0x1000>;
clock-names = "uart_clk", "pclk";
&i2c1 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
clock-frequency = <400000>;
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
eeprom: eeprom@50 { /* u46 - also at address 0x58 */
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
reg = <0x50>;
/* WP pin EE_WP_EN connected to slg7x644092@68 */
};
eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
reg = <0x51>;
};
};
zynqmp_ipi: zynqmp_ipi {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupt-parent = <&gic>;
interrupts = <0 35 4>;
ranges;
ipi_mailbox_pmu1: mailbox@ff990400 {
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x0 0xff9905c0 0x0 0x20>,
<0x0 0xff9905e0 0x0 0x20>,
<0x0 0xff990e80 0x0 0x20>,
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pmu {
compatible = "xlnx,zynqmp-firmware";
#power-domain-cells = <1>;
method = "smc";
- u-boot,dm-pre-reloc;
+ bootph-all;
zynqmp_power: zynqmp-power {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "xlnx,zynqmp-power";
interrupt-parent = <&gic>;
interrupts = <0 35 4>;
amba: axi {
compatible = "simple-bus";
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <2>;
#size-cells = <2>;
ranges;
};
qspi: spi@ff0f0000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "xlnx,zynqmp-qspi-1.0";
status = "disabled";
clock-names = "ref_clk", "pclk";
};
sdhci0: mmc@ff160000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
};
sdhci1: mmc@ff170000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
interrupt-parent = <&gic>;
};
uart0: serial@ff000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
};
uart1: serial@ff010000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
status = "disabled";
interrupt-parent = <&gic>;
};
zynqmp_dpsub: display@fd4a0000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "xlnx,zynqmp-dpsub-1.7";
status = "disabled";
reg = <0x0 0xfd4a0000 0x0 0x1000>,
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "qca,ar933x-pinctrl";
ranges;
#address-cells = <1>;
reg = <0x14e00000 0x4>;
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
cpu@0 {
compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
cpu@1 {
compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
periph_clk0: periph-clk@14e00004 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
memory-controller@12000000 {
compatible = "brcm,bcm6328-mc";
reg = <0x12000000 0x1000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
periph_rst0: reset-controller@14e0008c {
reg = <0x10000000 0x4>;
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
cpu@0 {
compatible = "brcm,bcm6318-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
hsspi_pll: hsspi-pll {
compatible = "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
periph_clk: periph-clk {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
periph_rst: reset-controller@10000010 {
compatible = "brcm,bcm6345-reset";
memory-controller@10004000 {
compatible = "brcm,bcm6318-mc";
reg = <0x10004000 0x38>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ehci: usb-controller@10005000 {
reg = <0x10000000 0x4>;
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
cpu@0 {
compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
cpu@1 {
compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
hsspi_pll: hsspi-pll {
compatible = "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
periph_clk: periph-clk {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
pll_cntl: syscon@10000008 {
compatible = "syscon";
memory-controller@10003000 {
compatible = "brcm,bcm6328-mc";
reg = <0x10003000 0x894>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
iudma: dma-controller@1000d800 {
reg = <0x10000000 0x4>;
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
cpu@0 {
compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
cpu@1 {
compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
hsspi_pll: hsspi-pll {
compatible = "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
periph_clk: periph-clk {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
periph_rst: reset-controller@10000010 {
compatible = "brcm,bcm6345-reset";
memory-controller@10003000 {
compatible = "brcm,bcm6328-mc";
reg = <0x10003000 0x864>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
iudma: dma-controller@1000d800 {
reg = <0xfffe0000 0x4>;
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
cpu@0 {
compatible = "brcm,bcm6338-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
periph_clk: periph-clk {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
pll_cntl: syscon@fffe0008 {
compatible = "syscon";
memory-controller@fffe3100 {
compatible = "brcm,bcm6338-mc";
reg = <0xfffe3100 0x38>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
iudma: dma-controller@fffe2400 {
reg = <0xfffe0000 0x4>;
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
cpu@0 {
compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
periph_clk: periph-clk {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
pll_cntl: syscon@fffe0008 {
compatible = "syscon";
memory-controller@fffe2300 {
compatible = "brcm,bcm6338-mc";
reg = <0xfffe2300 0x38>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
enet0: ethernet@fffe6000 {
reg = <0xfffe0000 0x4>;
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
cpu@0 {
compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
cpu@1 {
compatible = "brcm,bcm6358-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
periph_clk: periph-clk {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
pll_cntl: syscon@fffe0008 {
compatible = "syscon";
memory-controller@fffe1200 {
compatible = "brcm,bcm6358-mc";
reg = <0xfffe1200 0x4c>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ehci: usb-controller@fffe1300 {
reg = <0x10000000 0x4>;
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
cpu@0 {
compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
cpu@1 {
compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
hsspi_pll: hsspi-pll {
compatible = "fixed-clock";
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
periph_clk: periph-clk {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
pll_cntl: syscon@10000008 {
compatible = "syscon";
memory-controller@10003000 {
compatible = "brcm,bcm6328-mc";
reg = <0x10003000 0x864>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
iudma: dma-controller@1000d800 {
reg = <0x10000000 0x4>;
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
cpu@0 {
compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
cpu@1 {
compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
periph_clk: periph-clk {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
pll_cntl: syscon@10000008 {
compatible = "syscon";
memory-controller@10001200 {
compatible = "brcm,bcm6358-mc";
reg = <0x10001200 0x4c>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ehci: usb-controller@10001500 {
reg = <0x14e00000 0x4>;
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
cpu@0 {
compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
cpu@1 {
compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
device_type = "cpu";
reg = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
clocks {
compatible = "simple-bus";
- u-boot,dm-pre-reloc;
+ bootph-all;
periph_osc: periph-osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
memory: memory-controller@12000000 {
compatible = "brcm,bcm6328-mc";
reg = <0x12000000 0x1000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
gpio_test_port: syscon@14e00294 {
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
plat_regs: system-controller@17ffd000 {
compatible = "img,boston-platform-regs", "syscon";
reg = <0x17ffd000 0x1000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
clk_boston: clock {
compatible = "img,boston-clock";
#clock-cells = <1>;
regmap = <&plat_regs>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
reboot: syscon-reboot {
clocks = <&clk_boston BOSTON_CLK_SYS>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
lcd: lcd@17fff000 {
clk: clock {
compatible = "mrvl,octeon-clk";
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
gpio: gpio-controller@1070000000800 {
#size-cells = <0>;
compatible = "cavium,octeon-7xxx-l2c";
reg = <0x11800 0x80000000 0x0 0x01000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
lmc: lmc@1180088000000 {
#size-cells = <0>;
compatible = "cavium,octeon-7xxx-ddr4";
reg = <0x11800 0x88000000 0x0 0x02000000>; // 2 IFs
- u-boot,dm-pre-reloc;
+ bootph-all;
l2c-handle = <&l2c>;
};
};
&i2c0 {
- u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
+ bootph-all; /* Needed early for DDR SPD EEPROM */
clock-frequency = <100000>;
rtc@68 {
};
&i2c1 {
- u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
+ bootph-all; /* Needed early for DDR SPD EEPROM */
clock-frequency = <100000>;
};
};
&i2c0 {
- u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
+ bootph-all; /* Needed early for DDR SPD EEPROM */
clock-frequency = <100000>;
sfp0eeprom: eeprom@50 {
};
&i2c1 {
- u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
+ bootph-all; /* Needed early for DDR SPD EEPROM */
clock-frequency = <100000>;
vitesse@10 {
*/
&uartlite {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uartfull {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&sysc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&reboot {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clkctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rstctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&binman {
*/
&palmbus {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&reboot {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&clkctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rstctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
reg-names = "syscfg0", "clkcfg";
compatible = "mediatek,mt7628-clk";
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
rstctrl: rstctrl@0x34 {
clock-frequency = <1843200>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
microchip,refo4-frequency = <25000000>;
microchip,refo5-frequency = <40000000>;
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pinctrl {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart2 {
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdhci {
};
pinctrl {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "qca,qca953x-pinctrl";
ranges;
#address-cells = <1>;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
status = "okay";
};
#size-cells = <0>;
cpu: cpu@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
device_type = "cpu";
compatible = "altr,nios2-1.1";
reg = <0x00000000>;
cpus {
compatible = "cpu_bus";
- u-boot,dm-pre-reloc;
+ bootph-all;
PowerPC,8308@0 {
compatible = "fsl,mpc8308";
clocks = <&socclocks MPC83XX_CLK_CORE
&socclocks MPC83XX_CLK_CSB>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
socclocks: clocks {
compatible = "fsl,mpc8308-clk";
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
timer {
};
&board_soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
clocks = <&socclocks MPC83XX_CLK_CSB>;
memory@2000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
sdhc@2e000 {
};
&board_soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&GPIO_VB0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&serial0 {
clocks = <&socclocks MPC83XX_CLK_CSB>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&serial1 {
clocks = <&socclocks MPC83XX_CLK_CSB>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&pci0 {
/ {
cpus {
- u-boot,dm-pre-reloc;
+ bootph-all;
PowerPC,8321@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
&serial0 {
clock-frequency = <132000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
par_io@1400 {
compatible = "fsl,mpc8360-par_io";
- u-boot,dm-pre-reloc;
+ bootph-all;
serial_pin@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ucc_pin@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ucc_pin@1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ucc_pin@3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ucc_pin@4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ucc_pin@5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ucc_pin@6 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ucc_pin@7 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
/ {
cpus {
- u-boot,dm-pre-reloc;
+ bootph-all;
PowerPC,8360@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
par_io@1400 {
- u-boot,dm-pre-reloc;
+ bootph-all;
serial_pin@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ucc_pin@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ucc_pin@1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ucc_pin@3 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ucc_pin@4 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ucc_pin@5 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ucc_pin@6 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
ucc_pin@7 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&serial0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
soc@ffe000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
spi@110000 {
/* This documents where km_fpgacfg should be appear */
fpga@0 {
};
i2c@118000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
mux@70 {
i2c@1 { /* IVM bus */
reg = <1>;
};
serial@11c500 {
- u-boot,dm-pre-reloc;
+ bootph-all;
clock-frequency = <200000000>;
};
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x3000 0x100>;
interrupts = <43 2 0 0>;
dfsrr;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x3100 0x100>;
interrupts = <43 2 0 0>;
dfsrr;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x118000 0x100>;
interrupts = <38 2 0 0>;
};
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x118100 0x100>;
interrupts = <38 2 0 0>;
};
#size-cells = <0>;
cell-index = <2>;
compatible = "fsl-i2c";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x119000 0x100>;
interrupts = <39 2 0 0>;
};
#size-cells = <0>;
cell-index = <3>;
compatible = "fsl-i2c";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x119100 0x100>;
interrupts = <39 2 0 0>;
};
soc8544@e0000000 {
i2c@3000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
i2c_eeprom0: eeprom@51{
compatible = "atmel,24c64";
};
&serial0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
clock-frequency = <333333330>;
};
/ {
cpus {
- u-boot,dm-spl;
+ bootph-pre-ram;
CPU0: cpu@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
CPU0_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
CPU1: cpu@1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
CPU1_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
CPU2: cpu@2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
CPU2_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
CPU3: cpu@3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
CPU3_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
memory@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
plicsw: interrupt-controller@e6400000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
plmt0@e6000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
serial0: serial@f0300000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpus {
assigned-clocks = <&prci PRCI_CLK_COREPLL>;
assigned-clock-rates = <1000000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu0: cpu@0 {
clocks = <&prci PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
cpu0_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu1: cpu@1 {
clocks = <&prci PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu1_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu2: cpu@2 {
clocks = <&prci PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu2_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu3: cpu@3 {
clocks = <&prci PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu3_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu4: cpu@4 {
clocks = <&prci PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu4_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
otp: otp@10070000 {
compatible = "sifive,fu540-c000-otp";
reg = <0x0 0x10070000 0x0 0x1000>;
&cpu3_intc 3 &cpu3_intc 7
&cpu4_intc 3 &cpu4_intc 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
prci: clock-controller@10000000 {
#reset-cells = <1>;
0x0 0x100b8000 0x0 0x1000>;
clocks = <&prci PRCI_CLK_DDRPLL>;
clock-frequency = <933333324>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&prci {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&qspi2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
ð0 {
cpus {
assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>;
assigned-clock-rates = <1200000000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu0: cpu@0 {
clocks = <&prci FU740_PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
status = "okay";
cpu0_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu1: cpu@1 {
clocks = <&prci FU740_PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu1_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu2: cpu@2 {
clocks = <&prci FU740_PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu2_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu3: cpu@3 {
clocks = <&prci FU740_PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu3_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
cpu4: cpu@4 {
clocks = <&prci FU740_PRCI_CLK_COREPLL>;
- u-boot,dm-spl;
+ bootph-pre-ram;
cpu4_intc: interrupt-controller {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
soc {
- u-boot,dm-spl;
+ bootph-pre-ram;
clint: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
&cpu3_intc 3 &cpu3_intc 7
&cpu4_intc 3 &cpu4_intc 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
prci: clock-controller@10000000 {
#reset-cells = <1>;
0x0 0x100b8000 0x0 0x1000>;
clocks = <&prci FU740_PRCI_CLK_DDRPLL>;
clock-frequency = <933333324>;
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&prci {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&uart0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&spi0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
&i2c0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
ð0 {
};
memory@80000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
hfclk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
rtcclk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&qspi0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
flash@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&qspi2 {
mmc@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
memory@80000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
config {
};
hfclk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
rtcclk {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
};
&qspi0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
flash@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&spi0 {
mmc@0 {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
};
&gpio {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
<&sysclk K210_CLK_SRAM1>,
<&sysclk K210_CLK_AI>;
clock-names = "sram0", "sram1", "aisram";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
clocks {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
clocks = <&sysclk K210_CLK_APB1>;
clock-names = "pclk";
reg-io-width = <4>;
- u-boot,dm-pre-reloc;
+ bootph-all;
sysclk: clock-controller {
#clock-cells = <1>;
clocks = <&in0>;
assigned-clocks = <&sysclk K210_CLK_PLL1>;
assigned-clock-rates = <390000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
sysrst: reset-controller {
CPU0: cpu@0 {
clocks = <&clk0>;
- u-boot,dm-spl;
+ bootph-pre-ram;
device_type = "cpu";
reg = <0>;
compatible = "openhwgroup,cva6", "riscv";
};
memory@80000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
device_type = "memory";
reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >;
};
};
sdhci_0: sdhci@f000000000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "openpiton,piton-mmc", "openpiton,mmc";
reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >;
};
};
PLIC0: plic@fff1100000 {
- u-boot,dm-spl;
+ bootph-pre-ram;
#interrupt-cells = <1>;
compatible = "sifive,plic-1.0.0", "openpiton,plic";
interrupt-controller;
cros_ec: cros-ec {
reg = <0 0>;
- u-boot,dm-pre-proper;
+ bootph-some-ram;
compatible = "google,cros-ec-sandbox";
};
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pcic: pci@0 {
};
spi: spi@0 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0>;
};
clk_fixed: clk-fixed {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "sandbox,fixed-clock";
#clock-cells = <0>;
clock-frequency = <1234>;
};
clk_sandbox: clk-sbox {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "sandbox,clk";
#clock-cells = <1>;
assigned-clocks = <&clk_sandbox 3>;
};
clk-test {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "sandbox,clk-test";
clocks = <&clk_fixed>,
<&clk_sandbox 1>,
};
gpio_a: gpios@0 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
gpio-controller;
compatible = "sandbox,gpio";
#gpio-cells = <1>;
};
gpio_b: gpios@1 {
- u-boot,dm-spl;
+ bootph-pre-ram;
gpio-controller;
compatible = "sandbox,gpio";
#gpio-cells = <2>;
};
gpio-test {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "sandbox,gpio-test";
test-gpios = <&gpio_b 3 0>;
};
reg = <0x43>;
compatible = "sandbox-rtc";
sandbox,emul = <&emul0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
sandbox_pmic: sandbox_pmic {
reg = <0x40>;
};
i2c_emul: emul {
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0xff>;
compatible = "sandbox,i2c-emul-parent";
emul_eeprom: emul-eeprom {
#emul-cells = <0>;
};
emul0: emul0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "sandbox,i2c-rtc-emul";
#emul-cells = <0>;
};
};
irq_sandbox: irq-sbox {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "sandbox,irq";
interrupt-controller;
#interrupt-cells = <2>;
};
irq-test {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "sandbox,irq-test";
interrupts-extended = <&irq_sandbox 3 0>;
};
lcd {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
compatible = "sandbox,lcd-sdl";
xres = <1366>;
yres = <768>;
reset@1 {
compatible = "sandbox,reset";
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
rng {
spi@0 {
firmware_storage_spi: flash@0 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
reg = <0>;
compatible = "spansion,m25p16", "jedec,spi-nor";
spi-max-frequency = <40000000>;
};
spl-test {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "sandbox,spl-test";
boolval;
intval = <1>;
};
spl-test2 {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "sandbox,spl-test";
intval = <3>;
intarray = <5>;
};
spl-test3 {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "sandbox,spl-test";
stringarray = "one";
maybe-empty-int = <1>;
};
spl-test5 {
- u-boot,dm-vpl;
+ bootph-verify;
compatible = "sandbox,spl-test";
stringarray = "tpl";
};
spl-test6 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
compatible = "sandbox,spl-test";
stringarray = "pre-proper";
};
spl-test7 {
- u-boot,dm-spl;
+ bootph-pre-ram;
compatible = "sandbox,spl-test";
stringarray = "spl";
};
/* Needs to be available prior to relocation */
uart0: serial {
- u-boot,dm-spl;
- u-boot,dm-tpl;
- u-boot,dm-vpl;
+ bootph-pre-ram;
+ bootph-pre-sram;
+ bootph-verify;
compatible = "sandbox,serial";
sandbox,text-colour = "cyan";
pinctrl-names = "default";
};
keyboard-controller {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
};
/* ... */
cros_ec: cros-ec {
reg = <0 0 0 0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "google,cros-ec-sandbox";
};
};
spi: spi@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0 0 0>;
};
bootstd {
- u-boot,dm-vpl;
+ bootph-verify;
compatible = "u-boot,boot-std";
filename-prefixes = "/", "/boot/";
* before the parititon starts
*/
firmware0 {
- u-boot,dm-vpl;
+ bootph-verify;
compatible = "fwupd,vbe-simple";
storage = "mmc1";
skip-offset = <0x200>;
* running U-Boot
*/
firmware1 {
- u-boot,dm-vpl;
+ bootph-verify;
status = "disabled";
compatible = "fwupd,vbe-simple";
storage = "mmc3";
compatible = "denx,u-boot-fdt-test";
ping-expect = <0>;
ping-add = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
test-gpios = <&gpio_a 1>, <&gpio_a 4>,
<&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
<0>, <&gpio_a 12>;
};
lcd {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "sandbox,lcd-sdl";
pinctrl-names = "default";
pinctrl-0 = <&pinmux_lcd_pins>;
reg = <0x1>;
timebase-frequency = <3000000>;
compatible = "sandbox,cpu_sandbox";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
cpu2: cpu@2 {
device_type = "cpu";
reg = <0x2>;
compatible = "sandbox,cpu_sandbox";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
cpu3: cpu@3 {
device_type = "cpu";
reg = <0x3>;
compatible = "sandbox,cpu_sandbox";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
reset@0 {
compatible = "sandbox,warm-reset";
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
reset@1 {
compatible = "sandbox,reset";
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
resetc: reset-ctl {
uart0: serial {
compatible = "sandbox,serial";
- u-boot,dm-pre-reloc;
+ bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&pinmux_uart0_pins>;
};
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <60000000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
scif1: serial@ffe80000 {
clocks = <&scif_clks>;
clock-names = "fck";
status = "okay";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pci@fe200000 {
* CPUS are numbered sequentially from 0 using the device tree:
*
* cpus {
- * u-boot,dm-pre-reloc;
+ * bootph-all;
* #address-cells = <1>;
* #size-cells = <0>;
*
* cpu@0 {
- * u-boot,dm-pre-reloc;
+ * bootph-all;
* device_type = "cpu";
* compatible = "intel,apl-cpu";
* reg = <0>;
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0x20>;
bank-name = "A";
use-lvl-write-cache;
gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x20 0x20>;
bank-name = "B";
use-lvl-write-cache;
gpioc {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x40 0x20>;
bank-name = "C";
use-lvl-write-cache;
gpiod {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x60 0x20>;
bank-name = "D";
use-lvl-write-cache;
gpioe {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x80 0x20>;
bank-name = "E";
use-lvl-write-cache;
gpiof {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0xA0 0x20>;
bank-name = "F";
use-lvl-write-cache;
compatible = "intel,pci-baytrail", "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0x20>;
bank-name = "A";
use-lvl-write-cache;
gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x20 0x20>;
bank-name = "B";
use-lvl-write-cache;
gpioc {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x40 0x20>;
bank-name = "C";
use-lvl-write-cache;
gpiod {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x60 0x20>;
bank-name = "D";
use-lvl-write-cache;
gpioe {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x80 0x20>;
bank-name = "E";
use-lvl-write-cache;
gpiof {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0xA0 0x20>;
bank-name = "F";
use-lvl-write-cache;
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
clk: clock {
compatible = "intel,apl-clk";
#clock-cells = <1>;
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
cpus {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
#address-cells = <1>;
#size-cells = <0>;
cpu_0: cpu@0 {
- u-boot,dm-pre-proper;
- u-boot,dm-spl;
+ bootph-some-ram;
+ bootph-pre-ram;
device_type = "cpu";
compatible = "intel,apl-cpu";
reg = <0>;
};
acpi_gpe: general-purpose-events {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
compatible = "intel,acpi-gpe";
interrupt-controller;
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xefff>;
u-boot,skip-auto-config-until-reloc;
host_bridge: host-bridge@0,0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x00000000 0 0 0 0>;
compatible = "intel,apl-hostbridge";
pciex-region-size = <0x10000000>;
fsp_s: fsp-s {
};
fsp_m: fsp-m {
- u-boot,dm-spl;
+ bootph-pre-ram;
};
nhlt {
};
punit@0,1 {
- u-boot,dm-pre-proper;
- u-boot,dm-spl;
+ bootph-some-ram;
+ bootph-pre-ram;
reg = <0x00000800 0 0 0 0>;
compatible = "intel,apl-punit";
};
gma@2,0 {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
reg = <0x00001000 0 0 0 0>;
compatible = "fsp-fb";
};
p2sb: p2sb@d,0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x02006810 0 0 0 0>;
compatible = "intel,p2sb";
early-regs = <IOMAP_P2SB_BAR 0x100000>;
n {
compatible = "intel,apl-pinctrl";
- u-boot,dm-pre-reloc;
+ bootph-all;
intel,p2sb-port-id = <PID_GPIO_N>;
acpi,path = "\\_SB.GPO0";
gpio_n: gpio-n {
compatible = "intel,gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
gpio-controller;
#gpio-cells = <2>;
linux-name = "INT3452:00";
};
nw {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "intel,apl-pinctrl";
intel,p2sb-port-id = <PID_GPIO_NW>;
#gpio-cells = <2>;
acpi,path = "\\_SB.GPO1";
gpio_nw: gpio-nw {
compatible = "intel,gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
gpio-controller;
#gpio-cells = <2>;
linux-name = "INT3452:01";
};
w {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "intel,apl-pinctrl";
intel,p2sb-port-id = <PID_GPIO_W>;
#gpio-cells = <2>;
acpi,path = "\\_SB.GPO2";
gpio_w: gpio-w {
compatible = "intel,gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
gpio-controller;
#gpio-cells = <2>;
linux-name = "INT3452:02";
};
sw {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "intel,apl-pinctrl";
intel,p2sb-port-id = <PID_GPIO_SW>;
#gpio-cells = <2>;
acpi,path = "\\_SB.GPO3";
gpio_sw: gpio-sw {
compatible = "intel,gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
gpio-controller;
#gpio-cells = <2>;
linux-name = "INT3452:03";
};
itss {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "intel,itss";
intel,p2sb-port-id = <PID_ITSS>;
intel,pmc-routes = <
};
pmc@d,1 {
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x6900 0 0 0 0>;
/*
};
spi: fast-spi@d,2 {
- u-boot,dm-pre-proper;
- u-boot,dm-spl;
+ bootph-some-ram;
+ bootph-pre-ram;
reg = <0x02006a10 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
fwstore_spi: spi-flash@0 {
#size-cells = <1>;
#address-cells = <1>;
- u-boot,dm-pre-proper;
- u-boot,dm-spl;
+ bootph-some-ram;
+ bootph-pre-ram;
reg = <0>;
m25p,fast-read;
compatible = "winbond,w25q128fw",
rw-mrc-cache {
label = "rw-mrc-cache";
reg = <0x008e0000 0x00010000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
rw-var-mrc-cache {
label = "rw-mrc-cache";
reg = <0x008f0000 0x0001000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
compatible = "intel,apl-i2c", "snps,designware-i2c-pci";
reg = <0x0200b210 0 0 0 0>;
early-regs = <IOMAP_I2C2_BASE 0x1000>;
- u-boot,dm-pre-proper;
+ bootph-some-ram;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
tpm: tpm@50 {
reg = <0x50>;
compatible = "google,cr50";
- u-boot,dm-pre-proper;
+ bootph-some-ram;
u-boot,i2c-offset-len = <0>;
ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
interrupts-extended = <&acpi_gpe GPIO_28_IRQ
serial: serial@18,2 {
reg = <0x0200c210 0 0 0 0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "intel,apl-ns16550";
early-regs = <0xde000000 0x20>;
reg-shift = <2>;
pch: pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,apl-pch";
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <1>;
compatible = "intel,apl-lpc";
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
cros_ec: cros-ec {
- u-boot,dm-pre-proper;
- u-boot,dm-vpl;
+ bootph-some-ram;
+ bootph-verify;
compatible = "google,cros-ec-lpc";
reg = <0x204 1 0x200 1 0x880 0x80>;
};
&fsp_s {
- u-boot,dm-pre-proper;
+ bootph-some-ram;
fsps,ish-enable = <0>;
fsps,enable-sata = <0>;
&rtc {
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
pch_pinctrl {
compatible = "intel,x86-pinctrl";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0>;
gpio_a0 {
};
gpio_a10 {
- u-boot,dm-pre-reloc;
+ bootph-all;
gpio-offset = <0 10>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_b9 {
- u-boot,dm-pre-reloc;
+ bootph-all;
gpio-offset = <0x30 9>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_b10 {
- u-boot,dm-pre-reloc;
+ bootph-all;
gpio-offset = <0x30 10>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_b11 {
- u-boot,dm-pre-reloc;
+ bootph-all;
gpio-offset = <0x30 11>;
mode-gpio;
direction = <PIN_INPUT>;
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xefff>;
northbridge@0,0 {
reg = <0x00000000 0 0 0 0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "intel,bd82x6x-northbridge";
board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
<&gpio_b 11 0>, <&gpio_a 10 0>;
spd {
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <0>;
elpida_4Gb_1600_x16 {
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0>;
data = [92 10 0b 03 04 19 02 02
03 52 01 08 0a 00 fe 00
00 00 00 00 00 00 00 00];
};
samsung_4Gb_1600_1.35v_x16 {
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <1>;
data = [92 11 0b 03 04 19 02 02
03 11 01 08 0a 00 fe 00
me@16,0 {
reg = <0x0000b000 0 0 0 0>;
compatible = "intel,me";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
usb_1: usb@1a,0 {
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,bd82x6x", "intel,pch9";
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <1>;
intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
- u-boot,dm-pre-reloc;
+ bootph-all;
spi-flash@0 {
#size-cells = <1>;
#address-cells = <1>;
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0>;
m25p,fast-read;
compatible = "winbond,w25q64",
rw-mrc-cache {
label = "rw-mrc-cache";
reg = <0x003e0000 0x00010000>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
gpio_a: gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
#gpio-cells = <2>;
gpio-controller;
reg = <0 0x10>;
gpio_b: gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
#gpio-cells = <2>;
gpio-controller;
reg = <0x30 0x10>;
gpio_c: gpioc {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
#gpio-cells = <2>;
gpio-controller;
reg = <0x40 0x10>;
compatible = "intel,bd82x6x-lpc";
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
cros-ec@200 {
compatible = "google,cros-ec";
sata@1f,2 {
compatible = "intel,pantherpoint-ahci";
reg = <0x0000fa00 0 0 0 0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
intel,sata-mode = "ahci";
intel,sata-port-map = <1>;
intel,sata-port0-gen3-tx = <0x00880a7f>;
smbus: smbus@1f,3 {
compatible = "intel,ich-i2c";
reg = <0x0000fb00 0 0 0 0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
microcode {
- u-boot,dm-pre-reloc;
+ bootph-all;
update@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#include "microcode/m12306a9_0000001b.dtsi"
};
};
pch_pinctrl {
compatible = "intel,x86-broadwell-pinctrl";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0>;
/* Put this first: it is the default */
gpio_unused: gpio-unused {
- u-boot,dm-pre-reloc;
+ bootph-all;
mode-gpio;
direction = <PIN_INPUT>;
owner = <OWNER_GPIO>;
};
gpio_acpi_sci: acpi-sci {
- u-boot,dm-pre-reloc;
+ bootph-all;
mode-gpio;
direction = <PIN_INPUT>;
invert;
};
gpio_acpi_smi: acpi-smi {
- u-boot,dm-pre-reloc;
+ bootph-all;
mode-gpio;
direction = <PIN_INPUT>;
invert;
};
gpio_input: gpio-input {
- u-boot,dm-pre-reloc;
+ bootph-all;
mode-gpio;
direction = <PIN_INPUT>;
owner = <OWNER_GPIO>;
};
gpio_input_invert: gpio-input-invert {
- u-boot,dm-pre-reloc;
+ bootph-all;
mode-gpio;
direction = <PIN_INPUT>;
owner = <OWNER_GPIO>;
};
gpio_native: gpio-native {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
gpio_out_high: gpio-out-high {
- u-boot,dm-pre-reloc;
+ bootph-all;
mode-gpio;
direction = <PIN_OUTPUT>;
output-value = <1>;
};
gpio_out_low: gpio-out-low {
- u-boot,dm-pre-reloc;
+ bootph-all;
mode-gpio;
direction = <PIN_OUTPUT>;
output-value = <0>;
};
gpio_pirq: gpio-pirq {
- u-boot,dm-pre-reloc;
+ bootph-all;
mode-gpio;
direction = <PIN_INPUT>;
owner = <OWNER_GPIO>;
};
soc_gpio@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
config =
<0 &gpio_unused 0>, /* unused */
<1 &gpio_unused 0>, /* unused */
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xefff>;
compatible = "intel,broadwell-northbridge";
board-id-gpios = <&gpio_c 5 0>, <&gpio_c 4 0>,
<&gpio_c 3 0>, <&gpio_c 1 0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
spd {
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
samsung_4 {
reg = <6>;
- u-boot,dm-pre-reloc;
+ bootph-all;
data = [91 20 f1 03 04 11 05 0b
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
* columns 10, density 4096 mb, x32
*/
reg = <8>;
- u-boot,dm-pre-reloc;
+ bootph-all;
data = [91 20 f1 03 04 11 05 0b
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
};
samsung_8 {
reg = <10>;
- u-boot,dm-pre-reloc;
+ bootph-all;
data = [91 20 f1 03 04 12 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
* columns 11, density 4096 mb, x16
*/
reg = <12>;
- u-boot,dm-pre-reloc;
+ bootph-all;
data = [91 20 f1 03 04 12 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
* columns 11, density 8192 mb, x16
*/
reg = <13>;
- u-boot,dm-pre-reloc;
+ bootph-all;
data = [91 20 f1 03 05 1a 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
* columns 11, density 8192 mb, x16
*/
reg = <15>;
- u-boot,dm-pre-reloc;
+ bootph-all;
data = [91 20 f1 03 05 1a 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
me@16,0 {
reg = <0x0000b000 0 0 0 0>;
compatible = "intel,me";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
usb_0: usb@1d,0 {
pch: pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,broadwell-pch";
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <1>;
intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
power-enable-gpio = <&gpio_a 23 0>;
spi: spi {
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
fwstore_spi: spi-flash@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#size-cells = <1>;
#address-cells = <1>;
reg = <0>;
"jedec,spi-nor";
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
- u-boot,dm-pre-reloc;
+ bootph-all;
label = "rw-mrc-cache";
reg = <0x003e0000 0x00010000>;
};
gpio_a: gpioa {
compatible = "intel,broadwell-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
#gpio-cells = <2>;
gpio-controller;
reg = <0 0>;
gpio_b: gpiob {
compatible = "intel,broadwell-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
#gpio-cells = <2>;
gpio-controller;
reg = <1 0>;
gpio_c: gpioc {
compatible = "intel,broadwell-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
#gpio-cells = <2>;
gpio-controller;
reg = <2 0>;
compatible = "intel,broadwell-lpc";
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
cros_ec: cros-ec {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "google,cros-ec-lpc";
reg = <0x204 1 0x200 1 0x880 0x80>;
sata@1f,2 {
compatible = "intel,wildcatpoint-ahci";
reg = <0x0000fa00 0 0 0 0>;
- u-boot,dm-pre-proper;
+ bootph-some-ram;
intel,sata-mode = "ahci";
intel,sata-port-map = <1>;
intel,sata-port0-gen3-tx = <0x72>;
smbus: smbus@1f,3 {
compatible = "intel,ich-i2c";
reg = <0x0000fb00 0 0 0 0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
tpm {
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0xfed40000 0x5000>;
compatible = "infineon,slb9635lpc";
secdata {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "google,tpm-secdata";
};
};
microcode {
- u-boot,dm-pre-reloc;
+ bootph-all;
update@0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#include "microcode/mc0306d4_00000018.dtsi"
};
};
#address-cells = <1>;
#size-cells = <0>;
nvdata {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "google,cmos-nvdata";
reg = <0x26>;
};
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xf000>;
gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0x10>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x30 0x10>;
bank-name = "B";
};
gpioc {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x40 0x10>;
bank-name = "C";
};
compatible = "intel,pci-baytrail", "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0x20>;
bank-name = "A";
use-lvl-write-cache;
gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x20 0x20>;
bank-name = "B";
use-lvl-write-cache;
gpioc {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x40 0x20>;
bank-name = "C";
use-lvl-write-cache;
gpiod {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x60 0x20>;
bank-name = "D";
use-lvl-write-cache;
gpioe {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x80 0x20>;
bank-name = "E";
use-lvl-write-cache;
gpiof {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0xA0 0x20>;
bank-name = "F";
use-lvl-write-cache;
pci {
compatible = "pci-x86";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
serial: serial {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "coreboot-serial";
};
#address-cells = <3>;
#size-cells = <2>;
compatible = "pci-x86";
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,bd82x6x";
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <1>;
gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0x10>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x30 0x10>;
bank-name = "B";
};
gpioc {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x40 0x10>;
bank-name = "C";
};
#address-cells = <3>;
#size-cells = <2>;
compatible = "pci-x86";
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
#address-cells = <3>;
#size-cells = <2>;
compatible = "pci-bridge";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x0000b800 0x0 0x0 0x0 0x0>;
topcliff@0,0 {
#address-cells = <3>;
#size-cells = <2>;
compatible = "pci-bridge";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x00010000 0x0 0x0 0x0 0x0>;
pciuart0: uart@a,1 {
"pciclass,070002",
"pciclass,0700",
"ns16550";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x00025100 0x0 0x0 0x0 0x0
0x01025110 0x0 0x0 0x0 0x0>;
reg-shift = <0>;
"pciclass,070002",
"pciclass,0700",
"ns16550";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x00025200 0x0 0x0 0x0 0x0
0x01025210 0x0 0x0 0x0 0x0>;
reg-shift = <0>;
"pciclass,070002",
"pciclass,0700",
"ns16550";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x00025300 0x0 0x0 0x0 0x0
0x01025310 0x0 0x0 0x0 0x0>;
reg-shift = <0>;
"pciclass,070002",
"pciclass,0700",
"ns16550";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x00025400 0x0 0x0 0x0 0x0
0x01025410 0x0 0x0 0x0 0x0>;
reg-shift = <0>;
gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0x20>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x20 0x20>;
bank-name = "B";
};
compatible = "intel,pci-baytrail", "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
"pciclass,070002",
"pciclass,0700",
"ns16550";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x0200f310 0x0 0x0 0x0 0x0>;
reg-shift = <2>;
clock-frequency = <58982400>;
gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0x20>;
bank-name = "A";
use-lvl-write-cache;
gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x20 0x20>;
bank-name = "B";
use-lvl-write-cache;
gpioc {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x40 0x20>;
bank-name = "C";
use-lvl-write-cache;
gpiod {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x60 0x20>;
bank-name = "D";
use-lvl-write-cache;
gpioe {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x80 0x20>;
bank-name = "E";
use-lvl-write-cache;
gpiof {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0xA0 0x20>;
bank-name = "F";
use-lvl-write-cache;
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
reset {
compatible = "intel,reset-tangier";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
pinctrl {
reset {
compatible = "efi,reset";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
efi-fb {
compatible = "efi-fb";
pci {
compatible = "pci-x86";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
efi-fb {
#address-cells = <3>;
#size-cells = <2>;
compatible = "pci-x86";
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0x90000000 0x90000000 0 0x20000000
0x42000000 0x0 0xb0000000 0xb0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
"pciclass,070002",
"pciclass,0700",
"ns16550";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x0000a500 0x0 0x0 0x0 0x0
0x0200a510 0x0 0x0 0x0 0x0>;
reg-shift = <2>;
gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0x20>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x20 0x20>;
bank-name = "B";
};
compatible = "intel,pci-baytrail", "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
gpioa {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0 0x20>;
bank-name = "A";
use-lvl-write-cache;
gpiob {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x20 0x20>;
bank-name = "B";
use-lvl-write-cache;
gpioc {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x40 0x20>;
bank-name = "C";
use-lvl-write-cache;
gpiod {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x60 0x20>;
bank-name = "D";
use-lvl-write-cache;
gpioe {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0x80 0x20>;
bank-name = "E";
use-lvl-write-cache;
gpiof {
compatible = "intel,ich6-gpio";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0xA0 0x20>;
bank-name = "F";
use-lvl-write-cache;
cpus {
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
cpu@0 {
device_type = "cpu";
compatible = "cpu-qemu";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0>;
intel,apic-id = <0>;
};
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
pch@1,0 {
reg = <0x00000800 0 0 0 0>;
compatible = "intel,pch7";
- u-boot,dm-pre-reloc;
+ bootph-all;
irq-router {
compatible = "intel,irq-router";
- u-boot,dm-pre-reloc;
+ bootph-all;
intel,pirq-config = "pci";
intel,pirq-link = <0x60 4>;
intel,pirq-mask = <0x0e40>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
+ bootph-all;
cpu@0 {
device_type = "cpu";
compatible = "cpu-qemu";
- u-boot,dm-pre-reloc;
+ bootph-all;
reg = <0>;
intel,apic-id = <0>;
};
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,pch9";
- u-boot,dm-pre-reloc;
+ bootph-all;
irq-router {
compatible = "intel,irq-router";
- u-boot,dm-pre-reloc;
+ bootph-all;
intel,pirq-config = "pci";
intel,actl-8bit;
intel,actl-addr = <0x44>;
/ {
reset: reset {
compatible = "x86,reset";
- u-boot,dm-pre-proper;
+ bootph-some-ram;
};
};
/ {
rtc: rtc {
compatible = "motorola,mc146818";
- u-boot,dm-pre-proper;
+ bootph-some-ram;
reg = <0x70 2>;
};
};
/ {
serial: serial {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "ns16550";
reg = <0x3f8 8>;
reg-shift = <0>;
tsc-timer {
compatible = "x86,tsc-timer";
clock-frequency = <CONFIG_X86_TSC_TIMER_FREQ>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
projects / u-boot.git / commitdiff