riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode

The Andes PLMT driver directly accesses the mtime MMIO region,
indicating its intended use in the M-mode boot stage. However,
since U-Boot proper (S-mode) also uses the PLMT driver, we need
to specifically mark the region as readable through PMPCFGx (or
S/U-mode read-only shared data region for Smepmp) in OpenSBI.

Granting permission for this case doesn't make sense. Instead,
we should use the generic RISC-V timer driver to read the mtime
through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER
config, which ensures that the PLMT driver is linked exclusively
against M-mode U-Boot or U-Boot SPL binaries.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>

diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig
index 82bb5a2a5325c3ca5322d3bbc390d556da6b5304..f311291aedbb7f6ff6e455f871fb57498eb869ec 100644 (file)
--- a/arch/riscv/cpu/andesv5/Kconfig
+++ b/arch/riscv/cpu/andesv5/Kconfig
@@ -4,8 +4,9 @@ config RISCV_NDS
        imply CPU
        imply CPU_RISCV
        imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+       imply ANDES_PLMT_TIMER
+       imply SPL_ANDES_PLMT_TIMER
        imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
-       imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
        imply V5L2_CACHE
        imply SPL_CPU
        imply SPL_OPENSBI

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index a98be9dfae4ee2a7ecfd652e593a901612910d0f..60519c3b536cda11a0794c9979bab3fca46489a4 100644 (file)
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -59,7 +59,14 @@ config ALTERA_TIMER
 
 config ANDES_PLMT_TIMER
        bool
-       depends on RISCV_MMODE || SPL_RISCV_MMODE
+       depends on RISCV_MMODE
+       help
+         The Andes PLMT block holds memory-mapped mtime register
+         associated with timer tick.
+
+config SPL_ANDES_PLMT_TIMER
+       bool
+       depends on SPL_RISCV_MMODE
        help
          The Andes PLMT block holds memory-mapped mtime register
          associated with timer tick.

diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 1ef814970b9d0a62b920240985e5e7e76e47415e..b93145e8d437097d3c3c8f5903e8732f9703fb41 100644 (file)
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -4,7 +4,7 @@
 
 obj-y += timer-uclass.o
 obj-$(CONFIG_ALTERA_TIMER)     += altera_timer.o
-obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o
+obj-$(CONFIG_$(SPL_)ANDES_PLMT_TIMER) += andes_plmt_timer.o
 obj-$(CONFIG_ARC_TIMER)        += arc_timer.o
 obj-$(CONFIG_ARM_TWD_TIMER)    += arm_twd_timer.o
 obj-$(CONFIG_AST_TIMER)        += ast_timer.o