ARM: tegra: enable MIPI PAD CTRL support for Tegra124

This allows selection between CSI and DSI_B on the MIPI pads.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index 78bc9e6f178bf3fed86d7f84e615d0f68fc56c03..9fcbb0f80b4bb8d78b3e2660762b9752751aa291 100644 (file)
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -246,6 +246,11 @@ enum pmux_drvgrp {
        PMUX_DRVGRP_COUNT,
 };
 
+enum pmux_mipipadctrlgrp {
+       PMUX_MIPIPADCTRLGRP_DSI_B,
+       PMUX_MIPIPADCTRLGRP_COUNT,
+};
+
 enum pmux_func {
        PMUX_FUNC_DEFAULT,
        PMUX_FUNC_BLINK,
@@ -255,6 +260,7 @@ enum pmux_func {
        PMUX_FUNC_CLK,
        PMUX_FUNC_CLK12,
        PMUX_FUNC_CPU,
+       PMUX_FUNC_CSI,
        PMUX_FUNC_DAP,
        PMUX_FUNC_DAP1,
        PMUX_FUNC_DAP2,
@@ -263,6 +269,7 @@ enum pmux_func {
        PMUX_FUNC_DISPLAYA_ALT,
        PMUX_FUNC_DISPLAYB,
        PMUX_FUNC_DP,
+       PMUX_FUNC_DSI_B,
        PMUX_FUNC_DTV,
        PMUX_FUNC_EXTPERIPH1,
        PMUX_FUNC_EXTPERIPH2,
@@ -336,8 +343,10 @@ enum pmux_func {
 };
 
 #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
+#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820
 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING
 #define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
 #define TEGRA_PMX_GRPS_HAVE_LPMD
 #define TEGRA_PMX_GRPS_HAVE_SCHMT
 #define TEGRA_PMX_GRPS_HAVE_HSM

diff --git a/arch/arm/mach-tegra/tegra124/pinmux.c b/arch/arm/mach-tegra/tegra124/pinmux.c
index c6685eaae1e9817c4de448c2958722da201dbc8f..4629b4676c4a3cf19c5a887d7a50c19e888a1d79 100644 (file)
--- a/arch/arm/mach-tegra/tegra124/pinmux.c
+++ b/arch/arm/mach-tegra/tegra124/pinmux.c
@@ -304,3 +304,20 @@ static const struct pmux_pingrp_desc tegra124_pingroups[] = {
        PIN(DP_HPD_PFF0,            DP,         RSVD2,    RSVD3,        RSVD4),
 };
 const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups;
+
+#define MIPIPADCTRL_GRP(grp, f0, f1)   \
+       {                               \
+               .funcs = {              \
+                       PMUX_FUNC_##f0, \
+                       PMUX_FUNC_##f1, \
+               },                      \
+       }
+
+#define MIPIPADCTRL_RESERVED {}
+
+static const struct pmux_mipipadctrlgrp_desc tegra124_mipipadctrl_groups[] = {
+       /*              pin,   f0,  f1 */
+       /* Offset 0x820 */
+       MIPIPADCTRL_GRP(DSI_B, CSI, DSI_B),
+};
+const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups = tegra124_mipipadctrl_groups;