]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
Layerscape: Enable Job ring driver model.
authorGaurav Jain <gaurav.jain@nxp.com>
Thu, 24 Mar 2022 06:20:35 +0000 (11:50 +0530)
committerStefano Babic <sbabic@denx.de>
Tue, 12 Apr 2022 09:20:01 +0000 (11:20 +0200)
LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162
platforms are enabled with JR driver model.

removed sec_init() call from board files.
sec is initialized based on job ring information processed
from device tree.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
62 files changed:
arch/arm/cpu/armv7/ls102xa/cpu.c
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
board/freescale/ls1012afrdm/ls1012afrdm.c
board/freescale/ls1012aqds/ls1012aqds.c
board/freescale/ls1012ardb/ls1012ardb.c
board/freescale/ls1021aiot/ls1021aiot.c
board/freescale/ls1021aqds/ls1021aqds.c
board/freescale/ls1021atsn/ls1021atsn.c
board/freescale/ls1021atwr/ls1021atwr.c
board/freescale/ls1028a/ls1028a.c
board/freescale/ls1043ardb/ls1043ardb.c
board/freescale/ls1046afrwy/ls1046afrwy.c
board/freescale/ls1046aqds/ls1046aqds.c
board/freescale/ls1046ardb/ls1046ardb.c
board/freescale/ls1088a/ls1088a.c
board/freescale/ls2080aqds/ls2080aqds.c
board/freescale/ls2080ardb/ls2080ardb.c
board/freescale/lx2160a/lx2160a.c
board/kontron/sl28/sl28.c
configs/ls1021aiot_qspi_defconfig
configs/ls1021aiot_sdcard_defconfig
configs/ls1021aqds_ddr4_nor_defconfig
configs/ls1021aqds_ddr4_nor_lpuart_defconfig
configs/ls1021aqds_nand_defconfig
configs/ls1021aqds_nor_defconfig
configs/ls1021aqds_nor_lpuart_defconfig
configs/ls1021aqds_qspi_defconfig
configs/ls1021aqds_sdcard_ifc_defconfig
configs/ls1021aqds_sdcard_qspi_defconfig
configs/ls1021atsn_qspi_defconfig
configs/ls1021atsn_sdcard_defconfig
configs/ls1021atwr_nor_defconfig
configs/ls1021atwr_nor_lpuart_defconfig
configs/ls1021atwr_qspi_defconfig
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
configs/ls1021atwr_sdcard_ifc_defconfig
configs/ls1021atwr_sdcard_qspi_defconfig
configs/ls1043aqds_defconfig
configs/ls1043aqds_lpuart_defconfig
configs/ls1043aqds_nand_defconfig
configs/ls1043aqds_nor_ddr3_defconfig
configs/ls1043aqds_qspi_defconfig
configs/ls1043aqds_sdcard_ifc_defconfig
configs/ls1043aqds_sdcard_qspi_defconfig
configs/ls1043aqds_tfa_defconfig
configs/ls1043ardb_defconfig
configs/ls1043ardb_nand_defconfig
configs/ls1043ardb_sdcard_defconfig
configs/ls1043ardb_tfa_defconfig
configs/ls1046afrwy_tfa_defconfig
configs/ls1046aqds_defconfig
configs/ls1046aqds_lpuart_defconfig
configs/ls1046aqds_nand_defconfig
configs/ls1046aqds_qspi_defconfig
configs/ls1046aqds_sdcard_ifc_defconfig
configs/ls1046aqds_sdcard_qspi_defconfig
configs/ls1046aqds_tfa_defconfig
configs/ls1046ardb_emmc_defconfig
configs/ls1046ardb_qspi_defconfig
configs/ls1046ardb_qspi_spl_defconfig
configs/ls1046ardb_sdcard_defconfig
configs/ls1046ardb_tfa_defconfig

index d863c9625aa9f89ea016ec7a32d8a93b3b12639e..9fe1cd904876383c5afe04578612645fdfefd3d2 100644 (file)
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -20,6 +21,7 @@
 #include <config.h>
 #include <fsl_wdog.h>
 #include <linux/delay.h>
+#include <dm.h>
 
 #include "fsl_epu.h"
 
@@ -397,3 +399,19 @@ void arch_preboot_os(void)
        ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
        asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
 }
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+       if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+               struct udevice *dev;
+               int ret;
+
+               ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+               if (ret)
+                       printf("Failed to initialize %s: %d\n", dev->name, ret);
+       }
+
+       return 0;
+}
+#endif
index 177f568f26ee30b1830120c7c0e4037d29c05a5c..14678a367080bb652f76372cd798535a32c624af 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2021 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  */
 
@@ -49,6 +49,7 @@
 #endif
 #endif
 #include <linux/mii.h>
+#include <dm.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -1652,6 +1653,14 @@ __weak int serdes_misc_init(void)
 
 int arch_misc_init(void)
 {
+       if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+               struct udevice *dev;
+               int ret;
+
+               ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+               if (ret)
+                       printf("Failed to initialize %s: %d\n", dev->name, ret);
+       }
        serdes_misc_init();
 
        return 0;
index 5dd19cfcd9a5a4b0558246043302efdf73c36708..bc37c553a5b4f0730af30498a4cd5328c3038fd1 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2021 NXP
  */
 
 #include <common.h>
@@ -22,7 +22,6 @@
 #include <env_internal.h>
 #include <fsl_mmdc.h>
 #include <netdev.h>
-#include <fsl_sec.h>
 #include <net/pfe_eth/pfe/pfe_hw.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -172,10 +171,6 @@ int board_init(void)
        if (current_el() == 3)
                out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
        ppa_init();
 #endif
index 68578e81a5dcd96201c9d2d73d142c11b4abef32..361bd5c582a2074ecf3cb9d36c2f148d0334390f 100644 (file)
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -28,7 +29,6 @@
 #include <fsl_mmdc.h>
 #include <spl.h>
 #include <netdev.h>
-#include <fsl_sec.h>
 #include "../common/qixis.h"
 #include "ls1012aqds_qixis.h"
 #include "ls1012aqds_pfe.h"
@@ -150,10 +150,6 @@ int board_init(void)
        erratum_a010315();
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
        ppa_init();
 #endif
index 064fb4d39fad90d236d6810ded5bd9ace9d52372..456609d99324dc748fa5e97a52f1e66805d2b541 100644 (file)
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -27,7 +28,6 @@
 #include <env_internal.h>
 #include <fsl_mmdc.h>
 #include <netdev.h>
-#include <fsl_sec.h>
 #include <net/pfe_eth/pfe/pfe_hw.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -173,10 +173,6 @@ int board_init(void)
        erratum_a010315();
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
        ppa_init();
 #endif
index bfe61376042732a44833c98affe52b21d170ab9c..5ab03b33404142ec2c0343a2506c2a36d30d63b5 100644 (file)
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -209,10 +210,7 @@ int misc_init_r(void)
        device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 
 #endif
-
-#ifdef CONFIG_FSL_CAAM
-       return sec_init();
-#endif
+       return 0;
 }
 #endif
 
index 0647622cde5936c0d3505f89e78d3efe0f9c250c..2eaad9e74249a63939db0e94a3313276a0b92dea 100644 (file)
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
  */
 
 #include <common.h>
@@ -20,7 +20,6 @@
 #include <mmc.h>
 #include <fsl_csu.h>
 #include <fsl_ifc.h>
-#include <fsl_sec.h>
 #include <spl.h>
 #include <fsl_devdis.h>
 #include <fsl_validate.h>
@@ -388,9 +387,6 @@ int misc_init_r(void)
 
 #ifdef CONFIG_FSL_DEVICE_DISABLE
        device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
-#endif
-#ifdef CONFIG_FSL_CAAM
-       return sec_init();
 #endif
        return 0;
 }
index f31e16c419a9c05ab1edad535639e081dea7874c..f016088670f607540f6669812a7988ebc3b5cb89 100644 (file)
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2019 NXP
+/* Copyright 2016-2019, 2021 NXP
  */
 #include <common.h>
 #include <clock_legacy.h>
@@ -238,10 +238,7 @@ int misc_init_r(void)
 #ifdef CONFIG_FSL_DEVICE_DISABLE
        device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 #endif
-
-#ifdef CONFIG_FSL_CAAM
-       return sec_init();
-#endif
+       return 0;
 }
 #endif
 
index 4a24495673930ab4c7bc1dce0b8e81bdb3283c2c..a3aa84deb25150563fbbc61c85981a2c66835fe7 100644 (file)
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
  */
 
 #include <common.h>
@@ -26,7 +26,6 @@
 #include <netdev.h>
 #include <fsl_mdio.h>
 #include <tsec.h>
-#include <fsl_sec.h>
 #include <fsl_devdis.h>
 #include <spl.h>
 #include <linux/delay.h>
@@ -555,10 +554,7 @@ int misc_init_r(void)
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
        config_board_mux();
 #endif
-
-#ifdef CONFIG_FSL_CAAM
-       return sec_init();
-#endif
+       return 0;
 }
 #endif
 
index 486a544d3522b80e9a7b69f2f8a2b6c4bf2bc42b..71a086ef675b9c0b6c9f3418201c292c24d3f8e6 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
  */
 
 #include <common.h>
@@ -73,10 +73,6 @@ u32 get_lpuart_clk(void)
 
 int board_init(void)
 {
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
        ppa_init();
 #endif
index 1764c9336c0f0371fe4807dd6d97e72386149c5e..002869f43526ef2118d89f76f66c35fcba677c3a 100644 (file)
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -20,7 +21,6 @@
 #include <fm_eth.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
-#include <fsl_sec.h>
 #include "cpld.h"
 #ifdef CONFIG_U_QE
 #include <fsl_qe.h>
@@ -211,10 +211,6 @@ int board_init(void)
        out_le32(SMMU_NSCR0, val);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
        ppa_init();
 #endif
index f1c08a13f7bbc4497b363047752667c36367123d..5a298cd311e4924e75e95b3c7647b1ae6f0866cc 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
  */
 
 #include <common.h>
@@ -20,7 +20,6 @@
 #include <fm_eth.h>
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
-#include <fsl_sec.h>
 #include <fsl_dspi.h>
 #include "../common/i2c_mux.h"
 
@@ -135,10 +134,6 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
        out_le32(SMMU_NSCR0, val);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
-
        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
        return 0;
 }
index 8481c45a583ae314ae9cf4e39049deaa6a8fa0d7..e5b5441e2c3fd1901ee147da016916ec6fc44ea6 100644 (file)
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
  */
 
 #include <common.h>
@@ -28,7 +28,6 @@
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
-#include <fsl_sec.h>
 #include <spl.h>
 #include "../common/i2c_mux.h"
 
@@ -421,10 +420,6 @@ int board_init(void)
        out_le32(SMMU_NSCR0, val);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
-
        return 0;
 }
 
index f2949cf8b6959498b8d4947094826a32a653d8f2..05269fccd6abfe3087ced8c8fc8921e6d47289c3 100644 (file)
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -25,7 +26,6 @@
 #include <fsl_esdhc.h>
 #include <power/mc34vr500_pmic.h>
 #include "cpld.h"
-#include <fsl_sec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -96,10 +96,6 @@ int board_init(void)
        out_le32(SMMU_NSCR0, val);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
        ppa_init();
 #endif
index 63e824c3743d0ef939eec700020cbe63e14122f3..5bf13dcdeb3e6578a61e697f1dba05fedf794962 100644 (file)
@@ -13,7 +13,6 @@
 #include <netdev.h>
 #include <fsl_ifc.h>
 #include <fsl_ddr.h>
-#include <fsl_sec.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <fdt_support.h>
@@ -820,9 +819,6 @@ int board_init(void)
        out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
 #ifdef CONFIG_FSL_LS_PPA
        ppa_init();
 #endif
index 297629d5efb869e3cbaf8ac9dcb89a152217d3e8..5bdafebb6b11b2757cbce7d62d2c437ee66e618f 100644 (file)
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor
+ * Copyright 2021 NXP
  */
 #include <common.h>
 #include <clock_legacy.h>
@@ -21,7 +22,6 @@
 #include <rtc.h>
 #include <asm/arch/soc.h>
 #include <hwconfig.h>
-#include <fsl_sec.h>
 #include <asm/arch/ppa.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
 #include "../common/i2c_mux.h"
@@ -222,10 +222,6 @@ int board_init(void)
 #endif
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
        ppa_init();
 #endif
index 1975b0f47ddc47d115b250a0116b92a9c7b0592f..f5ebb934eb9722e7f28595e1f1daddf9f01c5884 100644 (file)
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor
- * Copyright 2017 NXP
+ * Copyright 2017, 2021 NXP
  */
 #include <common.h>
 #include <clock_legacy.h>
@@ -24,7 +24,6 @@
 #include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
 #include <asm/arch/ppa.h>
-#include <fsl_sec.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
 #include "../common/i2c_mux.h"
 
@@ -288,9 +287,6 @@ int board_init(void)
        QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
 #ifdef CONFIG_FSL_LS_PPA
        ppa_init();
 #endif
@@ -299,9 +295,6 @@ int board_init(void)
        /* invert AQR405 IRQ pins polarity */
        out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 #endif
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
 
 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
        pci_init();
index c9835f92999b93ae7d2a0b28cfe9daf4ede9d4b3..49d96d3fa2a97e9625950c119e492af2beea7289 100644 (file)
@@ -14,7 +14,6 @@
 #include <errno.h>
 #include <netdev.h>
 #include <fsl_ddr.h>
-#include <fsl_sec.h>
 #include <asm/io.h>
 #include <fdt_support.h>
 #include <linux/bitops.h>
@@ -593,10 +592,6 @@ int board_init(void)
        out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
-
 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
        pci_init();
 #endif
index 3c48a9141d0a8558103f2a51ac86bd0e90200205..17bb45773639b0215734dc40c2fc6219fd5d3cce 100644 (file)
@@ -31,9 +31,6 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-       if (CONFIG_IS_ENABLED(FSL_CAAM))
-               sec_init();
-
        return 0;
 }
 
index e0e72217d9a0833a2812104864a8f7b2032727bb..75cbb1a9bcedba882fb3ef5c06f7572f1507b13d 100644 (file)
@@ -43,6 +43,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 2a84f2d08674a58ef48dc24df7e4acdd11e02655..fd21d30258c98ad0d4f48335f1701ddc4938ffe2 100644 (file)
@@ -60,6 +60,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 500e277afc145411d512c2be32c6846a28bb57cb..30bb4ef031b32d64436731a6115e3db7052d5cac 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index 706d2a53532c28fae35d0ec3fd1f3106818d4af9..199432f1b7404f6aeed60bfa74578426ced6472e 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index 14082281ff85195dbbdb3accf71d12a0312ac91c..ba38a117538927fadb659b7892ea55edbd775602 100644 (file)
@@ -77,6 +77,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
index 8a98782e6b54b6029ea4049f57e75e1a1f4986fc..d4b49ad7335a294742e8982c4baea0aaeaeb5f19 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
index 807c8a3b3b90cc04145ee4f0e1dda29aa8d76f2e..5967f67deed5b663cf9433d3c4f7d7425f93ed0a 100644 (file)
@@ -57,6 +57,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
index 241627b7fc5d9e43dcdddd656d72ee7554a2e4f7..b1d121eb2c21bc7b3665933617dd079aa69a9d94 100644 (file)
@@ -55,6 +55,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index 5de980d1a3e0d3bc1363ca2129d07802ffb434ea..9dad52361700fd6ede5ab4e11087c728352a5efa 100644 (file)
@@ -75,6 +75,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
index 8706d68d976894a7a9a76b3c5528a59277aff90f..1da6ac5f37bd9752b7d67f6e8f47761d2a767fbd 100644 (file)
@@ -72,6 +72,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index f12c223bd1f203fc2d6d5dac2b6de9dafc312ef4..59d5b67227315fa7f71f28a23fdd49c13cccd59c 100644 (file)
@@ -38,6 +38,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index 5845017d66e19d2a87b280f81510337fb1e761b8..5dcdddc086039cc93cb1184e4ab61124781ff4c6 100644 (file)
@@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
index e9c3a8aba288f65986b6aa8ee5a1d4a5ebea6d71..8b65c3a3ba5edfb876d4a9791241f3593ada6759 100644 (file)
@@ -49,6 +49,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
index 0d9009e8fab4ebd1ed3215a34692e19109914d6d..ea1b0dd09b144d4c574cc8586e8daae0a7bb7d25 100644 (file)
@@ -49,6 +49,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
index 63534af160a8bbf98fce455ab5f15156ae7bafdb..27dcfdf39bf56433b2e000072ffaa789f8ab3100 100644 (file)
@@ -50,6 +50,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
index 3286196c50faf8e8cfbe2d9536132307c6962077..ba12760dfea3d5933d7deee9fa4083afebd1c4ee 100644 (file)
@@ -64,6 +64,7 @@ CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="ethernet@2d10000"
 CONFIG_DM=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_OF_CONTROL=y
 # CONFIG_SPL_BLK is not set
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
index c59486067917ce4eb5cb41e3a7b719276877540b..c949d97d097d6e93a9a00b7982d465a6ac9ed8ed 100644 (file)
@@ -67,6 +67,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
index 148fcb9753bff0fb49ce8c82324d87a930cd78c7..28fea7c3afd626432231d3b28d4db3e7cd0ad1b8 100644 (file)
@@ -67,6 +67,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
index 24eb2706e27c9008eb55c17a53ee2b2a4a7ed9c1..43d8b09b4b3c1810b6497e1a59bb306d680a55c8 100644 (file)
@@ -55,6 +55,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index 013b776919b6aa718d2f54cbe1e0342982d208e2..b17933958930f5088cb9478e184320ab8b90e952 100644 (file)
@@ -55,6 +55,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index ee584f8acea0d2332c2769e9cf613bce9741e05f..56f8a7795614ed7f80cc130ff644ebe8521d1f75 100644 (file)
@@ -74,6 +74,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index fd6a4945c88bdf3a06959fe7868b0c7b0e23fef5..358962d004edc4b6fd0e583dc8eed77b3325e49a 100644 (file)
@@ -55,6 +55,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
index 5d0743083378b6de81d030358740faf41a0db959..c166e3ebc7344faab486bb22ec539bfa03f8e781 100644 (file)
@@ -55,6 +55,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index 186004021393cd3ba95ec1337e57231a7579a165..91ab1b0e332baf1af040d55cdb6819cec2299143 100644 (file)
@@ -74,6 +74,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index e384e4a4245149fffa370f58114ce5aeace46167..d0dca3dfba17e99206525ea877dfd9d41aa4e2b9 100644 (file)
@@ -72,6 +72,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index 3ed054fd4ee62fad6acbcf22635ce150b476c2d2..5474a697eae9a302085af2f3135a895132b6be35 100644 (file)
@@ -62,6 +62,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index 4fb9d9395d091d2386c658adbbec56b1c6fb484d..a3485f044a0db7ae6fef5f5dd4ddd481460ec04d 100644 (file)
@@ -41,6 +41,7 @@ CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="FM1@DTSEC3"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_MPC8XXX_GPIO=y
index d8eb271608a23fafcbddf2c68b65ffdf765b4f46..65732c859ac50dd36f2404189350b271cb9c890c 100644 (file)
@@ -61,6 +61,7 @@ CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="FM1@DTSEC3"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
index 6c415ac187fbbcdd556dca35142b23994aa0bee9..9f0b7e25145f103ded577b395124230225631389 100644 (file)
@@ -61,6 +61,7 @@ CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="FM1@DTSEC3"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
index afcbe7032481a1b0323bff0df29a3101c9982cb7..c0c942c3175eaabfb4d89b54bb7c32f2f1a51a64 100644 (file)
@@ -45,6 +45,7 @@ CONFIG_USE_ETHPRIME=y
 CONFIG_ETHPRIME="FM1@DTSEC3"
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_MPC8XXX_GPIO=y
index 7cddc0c7d1ef3d8e89ced4ee15333732f9e4b682..d48b3640d9e5be0892b5bad6ed4788d250fba01b 100644 (file)
@@ -44,6 +44,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 # CONFIG_DDR_SPD is not set
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
index 7d7afc751c13d3297027c38589570f082b9a4bbf..3d4bf8febabe9d253cec2b2a9238082ba9f9fa43 100644 (file)
@@ -56,6 +56,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index cf767342b64e3dbfeb6cd4f9f8f6b404fa1b1d5f..06f6ee06b72fd29038ab5a97622702e23731379a 100644 (file)
@@ -56,6 +56,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index 209e07916642c26a1cab73e594bb23482db7ab57..49f1da41bdcfec5da1f2dbdb979a0b33ed737001 100644 (file)
@@ -75,6 +75,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index b5afc9757bcc894388572fb306a2ecbe00053b0e..e5485c5f7a950f284fc67304db9800ce1cab919b 100644 (file)
@@ -56,6 +56,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index 10e83f78b9b5ff12757a12f3d40e0fa7c4ee585a..05ee635ead96b4d88cb042625706001c85d83cb4 100644 (file)
@@ -76,6 +76,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index 5dc1b1fdf3721fb954d4464ae6c5613612aa0a5b..64459781810c53335208c1fe5ec0cbba2c156db0 100644 (file)
@@ -74,6 +74,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index c6fa99c240c777dda2317819ea316a17514f15be..3ce7c28cd6aea4f1c6c8263aeea747510a2d254b 100644 (file)
@@ -63,6 +63,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
index d6b6722274287ea733cdd7d652235704c5e99bf7..5ded57d8140ddc9322a7d054f84d28a37129f760 100644 (file)
@@ -64,6 +64,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_MPC8XXX_GPIO=y
index b21db08a84693bf8dbe939f611a2ce5e709f8a2b..63d9c7f6315a3ac66b53e70612b35dcbda05fc07 100644 (file)
@@ -51,6 +51,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_MPC8XXX_GPIO=y
index 49e5fb283b547a3d358ccc06993fdce63e82332b..fe0e63713509940c26ea068ea7fc1722b3f71837 100644 (file)
@@ -70,6 +70,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_MPC8XXX_GPIO=y
index d4c4a6a5b3c1df7fa29f09ade3bcfdb20b63d0ae..fffd14e175d2e7c6b336825b1e8ba65cedb034f1 100644 (file)
@@ -64,6 +64,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_MPC8XXX_GPIO=y
index 451c82235d24f8ef0814b80ca3cd70398aa422e0..0650662dfbf380feb55e7cd2899e349edf2dfec1 100644 (file)
@@ -49,6 +49,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_MPC8XXX_GPIO=y