// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <config.h>
#include <fsl_wdog.h>
#include <linux/delay.h>
+#include <dm.h>
#include "fsl_epu.h"
ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
+
+ return 0;
+}
+#endif
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2021 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*/
#endif
#endif
#include <linux/mii.h>
+#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
int arch_misc_init(void)
{
+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+ }
serdes_misc_init();
return 0;
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2021 NXP
*/
#include <common.h>
#include <env_internal.h>
#include <fsl_mmdc.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
if (current_el() == 3)
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <fsl_mmdc.h>
#include <spl.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
#include "ls1012aqds_pfe.h"
erratum_a010315();
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <env_internal.h>
#include <fsl_mmdc.h>
#include <netdev.h>
-#include <fsl_sec.h>
#include <net/pfe_eth/pfe/pfe_hw.h>
DECLARE_GLOBAL_DATA_PTR;
erratum_a010315();
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
#include <mmc.h>
#include <fsl_csu.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include <spl.h>
#include <fsl_devdis.h>
#include <fsl_validate.h>
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
-#endif
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
#endif
return 0;
}
// SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2019 NXP
+/* Copyright 2016-2019, 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
#include <netdev.h>
#include <fsl_mdio.h>
#include <tsec.h>
-#include <fsl_sec.h>
#include <fsl_devdis.h>
#include <spl.h>
#include <linux/delay.h>
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
config_board_mux();
#endif
-
-#ifdef CONFIG_FSL_CAAM
- return sec_init();
-#endif
+ return 0;
}
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
int board_init(void)
{
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <fm_eth.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include "cpld.h"
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include <common.h>
#include <fm_eth.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
-#include <fsl_sec.h>
#include <fsl_dspi.h>
#include "../common/i2c_mux.h"
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
return 0;
}
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
*/
#include <common.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
-#include <fsl_sec.h>
#include <spl.h>
#include "../common/i2c_mux.h"
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
return 0;
}
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <fsl_esdhc.h>
#include <power/mc34vr500_pmic.h>
#include "cpld.h"
-#include <fsl_sec.h>
DECLARE_GLOBAL_DATA_PTR;
out_le32(SMMU_NSCR0, val);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
#include <netdev.h>
#include <fsl_ifc.h>
#include <fsl_ddr.h>
-#include <fsl_sec.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <fdt_support.h>
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor
+ * Copyright 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
#include <rtc.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
-#include <fsl_sec.h>
#include <asm/arch/ppa.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"
#endif
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor
- * Copyright 2017 NXP
+ * Copyright 2017, 2021 NXP
*/
#include <common.h>
#include <clock_legacy.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <asm/arch/ppa.h>
-#include <fsl_sec.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/i2c_mux.h"
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
#include <errno.h>
#include <netdev.h>
#include <fsl_ddr.h>
-#include <fsl_sec.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <linux/bitops.h>
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
-
#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
pci_init();
#endif
int board_init(void)
{
- if (CONFIG_IS_ENABLED(FSL_CAAM))
- sec_init();
-
return 0;
}
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_ETHPRIME="ethernet@2d10000"
CONFIG_DM=y
CONFIG_SPL_DM=y
+CONFIG_SPL_OF_CONTROL=y
# CONFIG_SPL_BLK is not set
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DDR_ECC=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
# CONFIG_DDR_SPD is not set
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
# CONFIG_DDR_SPD is not set
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y