global: Remove unused or unnecessary CONFIG symbols related to DDR

These symbols are now either unused or were only used within the config
file to determine other logic, which could be done in a way that doesn't
further pollute the CONFIG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
index a861e8dd2ddcfe05b3ce2522678414daf2c8530f..e12043b260935d4b7b579149135b36581b673a8d 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c
+++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c
@@ -834,12 +834,6 @@ long int spd_sdram()
 #endif
        debug("   DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
 
-#if defined(CONFIG_DDR_2T_TIMING)
-       /*
-        * Enable 2T timing by setting sdram_cfg[16].
-        */
-       sdram_cfg |= SDRAM_CFG_2T_EN;
-#endif
        /* Enable controller, and GO! */
        ddr->sdram_cfg = sdram_cfg;
        sync();
@@ -914,16 +908,12 @@ void ddr_enable_ecc(unsigned int dram_size)
        pattern[0] = 0xdeadbeef;
        pattern[1] = 0xdeadbeef;
 
-#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
-       dma_meminit(pattern[0], dram_size);
-#else
        debug("ddr init: CPU FP write method\n");
        size = dram_size;
        for (p = 0; p < (u64*)(size); p++) {
                ppcDWstore((u32*)p, pattern);
        }
        sync();
-#endif
 
        t_end = get_tbms();
        icache_disable();

diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 2c96378efef81b63b16e56ce92eb53bdaaa382b5..2a78551ce39ced4e5f64e6c267086094593fd44d 100644 (file)
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -28,8 +28,7 @@
 
 /* Check if boards need to enable FSL DMA engine for SDRAM init */
 #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
-#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
-       ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
+#if ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
        !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
 #define CONFIG_FSL_DMA
 #endif

diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index c4c7f528b58ea6e8af317c0b36ec7b7eb8a5956f..eff248104dc0b0d63b859af0ae61301ba127aff4 100644 (file)
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -100,21 +100,6 @@ int fixed_sdram(void)
 #if (CONFIG_SYS_DDR_SIZE != 256)
 #warning Currenly any ddr size other than 256 is not supported
 #endif
-#ifdef CONFIG_DDR_II
-       im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
-       im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
-       im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
-       im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
-       im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-       im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
-       im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
-       im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
-       im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
-       im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
-       im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-       im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
-#else
-
 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
 #warning Chip select bounds is only configurable in 16MB increments
 #endif
@@ -134,18 +119,10 @@ int fixed_sdram(void)
 
        im->ddr.sdram_cfg =
                SDRAM_CFG_SREN
-#if defined(CONFIG_DDR_2T_TIMING)
-               | SDRAM_CFG_2T_EN
-#endif
                | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
-#if defined (CONFIG_DDR_32BIT)
-       /* for 32-bit mode burst length is 8 */
-       im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
-#endif
        im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 
        im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-#endif
        udelay(200);
 
        /* enable DDR controller */

diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c
index b7eddf0f04c5d377fe47d2d42b92fe396be76144..1864b5d88b08b36e889ca47a80f0ab623ac617f7 100644 (file)
--- a/drivers/dma/fsl_dma.c
+++ b/drivers/dma/fsl_dma.c
@@ -130,11 +130,9 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
 
 /*
  * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER
- * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA
  */
 #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) &&    \
-       !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) ||         \
-       (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
+       !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)))
 void dma_meminit(uint val, uint size)
 {
        uint *p = 0;

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index d5af4e8166aaf31bc89edb31051ba095c803305e..9e487b8da2957d841b27c92a4a38c2b8c02665dc 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -38,23 +38,9 @@
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE  0xDeadBeef
 
-/*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
- */
-#undef CONFIG_DDR_32BIT
-
 #define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory*/
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#undef  CONFIG_DDR_2T_TIMING
-
 /*
  * DDRCDR - DDR Control Driver Register
  */
@@ -70,21 +56,6 @@
  * Manually set up DDR parameters
  */
 #define CONFIG_SYS_DDR_SIZE            256             /* MB */
-#if defined(CONFIG_DDR_II)
-#define CONFIG_SYS_DDRCDR              0x80080001
-#define CONFIG_SYS_DDR_CS2_BNDS                0x0000000f
-#define CONFIG_SYS_DDR_CS2_CONFIG      0x80330102
-#define CONFIG_SYS_DDR_TIMING_0                0x00220802
-#define CONFIG_SYS_DDR_TIMING_1                0x38357322
-#define CONFIG_SYS_DDR_TIMING_2                0x2f9048c8
-#define CONFIG_SYS_DDR_TIMING_3                0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL                0x02000000
-#define CONFIG_SYS_DDR_MODE            0x47d00432
-#define CONFIG_SYS_DDR_MODE2           0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL                0x03cf0080
-#define CONFIG_SYS_DDR_SDRAM_CFG       0x43000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2      0x00401000
-#else
 #define CONFIG_SYS_DDR_CS2_CONFIG      (CSCONFIG_EN \
                                | CSCONFIG_ROW_BIT_13 \
                                | CSCONFIG_COL_BIT_10)
@@ -93,17 +64,10 @@
 #define CONFIG_SYS_DDR_CONTROL 0xc2000000      /* unbuffered,no DYN_PWR */
 #define CONFIG_SYS_DDR_INTERVAL        0x04060100      /* autocharge,no open page */
 
-#if defined(CONFIG_DDR_32BIT)
-/* set burst length to 8 for 32-bit data path */
-                               /* DLL,normal,seq,4/2.5, 8 burst len */
-#define CONFIG_SYS_DDR_MODE    0x00000023
-#else
 /* the default burst length is 4 - for 64-bit data path */
                                /* DLL,normal,seq,4/2.5, 4 burst len */
 #define CONFIG_SYS_DDR_MODE    0x00000022
 #endif
-#endif
-#endif
 
 /*
  * SDRAM on the Local Bus

diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index ac12b22e64e282efe453640d97b7ed08c3552d25..e652309da58aab014e0e0c485e03dfaae3bd8c98 100644 (file)
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -38,23 +38,9 @@
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE  0xDeadBeef
 
-/*
- * 32-bit data path mode.
- *
- * Please note that using this mode for devices with the real density of 64-bit
- * effectively reduces the amount of available memory due to the effect of
- * wrapping around while translating address to row/columns, for example in the
- * 256MB module the upper 128MB get aliased with contents of the lower
- * 128MB); normally this define should be used for devices with real 32-bit
- * data path.
- */
-#undef CONFIG_DDR_32BIT
-
 #define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory*/
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
-#undef  CONFIG_DDR_2T_TIMING
-
 /*
  * DDRCDR - DDR Control Driver Register
  */
@@ -70,21 +56,6 @@
  * Manually set up DDR parameters
  */
 #define CONFIG_SYS_DDR_SIZE            256             /* MB */
-#if defined(CONFIG_DDR_II)
-#define CONFIG_SYS_DDRCDR              0x80080001
-#define CONFIG_SYS_DDR_CS2_BNDS                0x0000000f
-#define CONFIG_SYS_DDR_CS2_CONFIG      0x80330102
-#define CONFIG_SYS_DDR_TIMING_0                0x00220802
-#define CONFIG_SYS_DDR_TIMING_1                0x38357322
-#define CONFIG_SYS_DDR_TIMING_2                0x2f9048c8
-#define CONFIG_SYS_DDR_TIMING_3                0x00000000
-#define CONFIG_SYS_DDR_CLK_CNTL                0x02000000
-#define CONFIG_SYS_DDR_MODE            0x47d00432
-#define CONFIG_SYS_DDR_MODE2           0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL                0x03cf0080
-#define CONFIG_SYS_DDR_SDRAM_CFG       0x43000000
-#define CONFIG_SYS_DDR_SDRAM_CFG2      0x00401000
-#else
 #define CONFIG_SYS_DDR_CS2_CONFIG      (CSCONFIG_EN \
                                | CSCONFIG_ROW_BIT_13 \
                                | CSCONFIG_COL_BIT_10)
@@ -93,17 +64,10 @@
 #define CONFIG_SYS_DDR_CONTROL 0xc2000000      /* unbuffered,no DYN_PWR */
 #define CONFIG_SYS_DDR_INTERVAL        0x04060100      /* autocharge,no open page */
 
-#if defined(CONFIG_DDR_32BIT)
-/* set burst length to 8 for 32-bit data path */
-                               /* DLL,normal,seq,4/2.5, 8 burst len */
-#define CONFIG_SYS_DDR_MODE    0x00000023
-#else
 /* the default burst length is 4 - for 64-bit data path */
                                /* DLL,normal,seq,4/2.5, 4 burst len */
 #define CONFIG_SYS_DDR_MODE    0x00000022
 #endif
-#endif
-#endif
 
 /*
  * SDRAM on the Local Bus

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 1d2389a1c60702fe2269841caf49f8b556c6c88a..5d5efd0967802b7cfa39657815297d76aa7d1c4e 100644 (file)
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -113,17 +113,9 @@
                                | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
                                /* 0x06090100 */
 
-#if defined(CONFIG_DDR_2T_TIMING)
-#define CONFIG_SYS_DDR_SDRAM_CFG       (SDRAM_CFG_SREN \
-                                       | SDRAM_CFG_SDRAM_TYPE_DDR2 \
-                                       | SDRAM_CFG_32_BE \
-                                       | SDRAM_CFG_2T_EN)
-                                       /* 0x43088000 */
-#else
 #define CONFIG_SYS_DDR_SDRAM_CFG       (SDRAM_CFG_SREN \
                                        | SDRAM_CFG_SDRAM_TYPE_DDR2)
                                        /* 0x43000000 */
-#endif
 #define CONFIG_SYS_DDR_SDRAM_CFG2      0x00001000 /* 1 posted refresh */
 #define CONFIG_SYS_DDR_MODE            ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
                                        | (0x0442 << SDRAM_MODE_SD_SHIFT))

diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 86bfc746d8748687afc2f0ba2e8cc3dcece262d8..a3caee4254b8d8a63ccb27f4140a8af29db3cfe0 100644 (file)
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -171,11 +171,6 @@
 #endif
 
 /* DDR Setup */
-#define CONFIG_DDR_ECC_ENABLE
-#ifndef CONFIG_DDR_ECC_ENABLE
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
-#endif
 #define CONFIG_SYS_SPD_BUS_NUM 1
 
 #define CONFIG_SYS_SDRAM_SIZE_LAW      LAW_SIZE_512M
@@ -204,11 +199,7 @@
 #define CONFIG_SYS_DDR_SR_CNTR         0x00000000
 #define CONFIG_SYS_DDR_RCW_1           0x00000000
 #define CONFIG_SYS_DDR_RCW_2           0x00000000
-#ifdef CONFIG_DDR_ECC_ENABLE
 #define CONFIG_SYS_DDR_CONTROL         0xE70C0000      /* Type = DDR3 & ECC */
-#else
-#define CONFIG_SYS_DDR_CONTROL         0xC70C0000      /* Type = DDR3 */
-#endif
 #define CONFIG_SYS_DDR_CONTROL_2       0x04401050
 #define CONFIG_SYS_DDR_TIMING_4                0x00220001
 #define CONFIG_SYS_DDR_TIMING_5                0x03402400

diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h
index 05bb51f545e76ace2668266715418af7d3c2019d..45db5cf873c78796d055a5c373791df51dad846e 100644 (file)
--- a/include/configs/km/km-mpc83xx.h
+++ b/include/configs/km/km-mpc83xx.h
@@ -18,7 +18,6 @@
 /*
  * Manually set up DDR parameters
  */
-#define CONFIG_DDR_II
 #define CONFIG_SYS_DDR_SIZE            2048 /* MB */
 
 /*

diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 131f61478276d02bfe742d7ba16b002539706d82..bca5b6af92c04568f0c4b6d0f1c5e319e88a8452 100644 (file)
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -72,7 +72,6 @@
 /* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS     0x50    /* CTLR 0 DIMM 0 */
 
-#define CONFIG_DDR_DEFAULT_CL  30              /* CAS latency 3        */
 
 /* Hardcoded values, to use instead of SPD */
 #define CONFIG_SYS_DDR_CS0_BNDS                0x0000000f

diff --git a/post/cpu/mpc83xx/ecc.c b/post/cpu/mpc83xx/ecc.c
index cc971a8909784c9d4be997a14e422716b4d631b5..f88eff8998f9184085b83a396df6f82c820a1348 100644 (file)
--- a/post/cpu/mpc83xx/ecc.c
+++ b/post/cpu/mpc83xx/ecc.c
@@ -70,10 +70,6 @@ int ecc_post_test(int flags)
        int_state = disable_interrupts();
        icache_enable();
 
-#ifdef CONFIG_DDR_32BIT
-       /* It seems like no one really uses the CONFIG_DDR_32BIT mode */
-#error "Add ECC POST support for CONFIG_DDR_32BIT here!"
-#else
        for (addr = (u64*)CONFIG_SYS_POST_ECC_START_ADDR, errbit=0;
             addr < (u64*)CONFIG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) {
 
@@ -138,7 +134,6 @@ int ecc_post_test(int flags)
 
                errbit %= 63;
        }
-#endif /* !CONFIG_DDR_32BIT */
 
        ecc_clear(ddr);