Layerscape: Add crypto node in device tree

LS(1021/1012/1028/1043/1046/1088/2088), LX2160 - updated device tree

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>

diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 0ea899c7d7c58405b2c966b56ac45135f326b4f7..1cdcc99c1ee65a4f077e04dd9ef13e2cefa12eec 100644 (file)
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  * Copyright 2016 Freescale Semiconductor
  */
 
@@ -71,6 +71,50 @@
                        bus-width = <4>;
                };
 
+               crypto: crypto@1700000 {
+                       compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+                                    "fsl,sec-v4.0";
+                       fsl,sec-era = <8>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x00 0x1700000 0x100000>;
+                       reg = <0x00 0x1700000 0x0 0x100000>;
+                       interrupts = <0 75 0x4>;
+                       dma-coherent;
+
+                       sec_jr0: jr@10000 {
+                               compatible = "fsl,sec-v5.4-job-ring",
+                                            "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg        = <0x10000 0x10000>;
+                               interrupts = <0 71 0x4>;
+                       };
+
+                       sec_jr1: jr@20000 {
+                               compatible = "fsl,sec-v5.4-job-ring",
+                                            "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg        = <0x20000 0x10000>;
+                               interrupts = <0 72 0x4>;
+                       };
+
+                       sec_jr2: jr@30000 {
+                               compatible = "fsl,sec-v5.4-job-ring",
+                                            "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg        = <0x30000 0x10000>;
+                               interrupts = <0 73 0x4>;
+                       };
+
+                       sec_jr3: jr@40000 {
+                               compatible = "fsl,sec-v5.4-job-ring",
+                                            "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg        = <0x40000 0x10000>;
+                               interrupts = <0 74 0x4>;
+                       };
+               };
+
                gpio0: gpio@2300000 {
                        compatible = "fsl,qoriq-gpio";
                        reg = <0x0 0x2300000 0x0 0x10000>;

diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 52dc5a9638241295ea504f34d00b78c79a5f492c..72877d2ff58e5201e529236c468b25c576095ff0 100644 (file)
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -2,7 +2,7 @@
 /*
  * Device Tree Include file for NXP Layerscape-1043A family SoC.
  *
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  * Copyright (C) 2014-2015, Freescale Semiconductor
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
@@ -125,6 +125,49 @@
                        interrupts = <0 43 0x4>;
                };
 
+               crypto: crypto@1700000 {
+                       compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+                                    "fsl,sec-v4.0";
+                       fsl,sec-era = <3>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x00 0x1700000 0x100000>;
+                       reg = <0x00 0x1700000 0x0 0x100000>;
+                       interrupts = <0 75 0x4>;
+
+                       sec_jr0: jr@10000 {
+                               compatible = "fsl,sec-v5.4-job-ring",
+                                            "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg        = <0x10000 0x10000>;
+                               interrupts = <0 71 0x4>;
+                       };
+
+                       sec_jr1: jr@20000 {
+                               compatible = "fsl,sec-v5.4-job-ring",
+                                            "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg        = <0x20000 0x10000>;
+                               interrupts = <0 72 0x4>;
+                       };
+
+                       sec_jr2: jr@30000 {
+                               compatible = "fsl,sec-v5.4-job-ring",
+                                            "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg        = <0x30000 0x10000>;
+                               interrupts = <0 73 0x4>;
+                       };
+
+                       sec_jr3: jr@40000 {
+                               compatible = "fsl,sec-v5.4-job-ring",
+                                            "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg        = <0x40000 0x10000>;
+                               interrupts = <0 74 0x4>;
+                       };
+               };
+
                i2c0: i2c@2180000 {
                        compatible = "fsl,vf610-i2c";
                        #address-cells = <1>;

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index a60cbf11fc56c05377e8c99d7b0e1397b8913dc4..c655e002aa0825e56b51186cee9438dd66f379ef 100644 (file)
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -3,6 +3,7 @@
  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
  *
  * Copyright (C) 2016, Freescale Semiconductor
+ * Copyright 2021 NXP
  *
  * Mingkai Hu <mingkai.hu@nxp.com>
  */
@@ -124,6 +125,49 @@
                        interrupts = <0 43 0x4>;
                };
 
+               crypto: crypto@1700000 {
+                       compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+                                    "fsl,sec-v4.0";
+                       fsl,sec-era = <8>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x00 0x1700000 0x100000>;
+                       reg = <0x00 0x1700000 0x0 0x100000>;
+                       interrupts = <0 75 0x4>;
+
+                       sec_jr0: jr@10000 {
+                               compatible = "fsl,sec-v5.4-job-ring",
+                                            "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg        = <0x10000 0x10000>;
+                               interrupts = <0 71 0x4>;
+                       };
+
+                       sec_jr1: jr@20000 {
+                               compatible = "fsl,sec-v5.4-job-ring",
+                                            "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg        = <0x20000 0x10000>;
+                               interrupts = <0 72 0x4>;
+                       };
+
+                       sec_jr2: jr@30000 {
+                               compatible = "fsl,sec-v5.4-job-ring",
+                                            "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg        = <0x30000 0x10000>;
+                               interrupts = <0 73 0x4>;
+                       };
+
+                       sec_jr3: jr@40000 {
+                               compatible = "fsl,sec-v5.4-job-ring",
+                                            "fsl,sec-v5.0-job-ring",
+                                            "fsl,sec-v4.0-job-ring";
+                               reg        = <0x40000 0x10000>;
+                               interrupts = <0 74 0x4>;
+                       };
+               };
+
                i2c0: i2c@2180000 {
                        compatible = "fsl,vf610-i2c";
                        #address-cells = <1>;

diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index f73fdfda8b51eb06fc2319b316b4371867af0439..9b7c54b260e21cfdc8673b18477de5e095ccaa35 100644 (file)
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -174,6 +174,45 @@
                dr_mode = "host";
        };
 
+       crypto: crypto@8000000 {
+               compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+               fsl,sec-era = <8>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x00 0x8000000 0x100000>;
+               reg = <0x00 0x8000000 0x0 0x100000>;
+               interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+               dma-coherent;
+
+               sec_jr0: jr@10000 {
+                       compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                       reg        = <0x10000 0x10000>;
+                       interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               sec_jr1: jr@20000 {
+                       compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                       reg        = <0x20000 0x10000>;
+                       interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               sec_jr2: jr@30000 {
+                       compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                       reg        = <0x30000 0x10000>;
+                       interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               sec_jr3: jr@40000 {
+                       compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                       reg        = <0x40000 0x10000>;
+                       interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+               };
+       };
+
        pcie1: pcie@3400000 {
                compatible = "fsl,ls-pcie", "snps,dw-pcie";
                reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */

diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 72ba52594a18e8b1bccac1bc060d8e0781d855ae..a1837454f43de62db5bbb851f0a5006a96e6adc3 100644 (file)
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -239,6 +239,45 @@
                        status = "disabled";
        };
 
+       crypto: crypto@8000000 {
+               compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+               fsl,sec-era = <8>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x00 0x8000000 0x100000>;
+               reg = <0x00 0x8000000 0x0 0x100000>;
+               interrupts = <0 139 0x4>;  /* Level high type */
+               dma-coherent;
+
+               sec_jr0: jr@10000 {
+                       compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                       reg        = <0x10000 0x10000>;
+                       interrupts = <0 140 0x4>;  /* Level high type */
+               };
+
+               sec_jr1: jr@20000 {
+                       compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                       reg        = <0x20000 0x10000>;
+                       interrupts = <0 141 0x4>;  /* Level high type */
+               };
+
+               sec_jr2: jr@30000 {
+                       compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                       reg        = <0x30000 0x10000>;
+                       interrupts = <0 142 0x4>;  /* Level high type */
+               };
+
+               sec_jr3: jr@40000 {
+                       compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                       reg        = <0x40000 0x10000>;
+                       interrupts = <0 143 0x4>;  /* Level high type */
+               };
+       };
+
        fsl_mc: fsl-mc@80c000000 {
                compatible = "fsl,qoriq-mc", "simple-mfd";
                reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */

diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 52e4d7205a2647abcc2ad3849807045bf126d79e..57c7d3ef71111d67f337870f16cc9e479bfb1990 100644 (file)
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP lx2160a SOC common device tree source
  *
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
  *
  */
 
@@ -27,6 +27,45 @@
                clock-output-names = "sysclk";
        };
 
+       crypto: crypto@8000000 {
+               compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+               fsl,sec-era = <10>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x00 0x8000000 0x100000>;
+               reg = <0x00 0x8000000 0x0 0x100000>;
+               interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+               dma-coherent;
+
+               sec_jr0: jr@10000 {
+                       compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                       reg        = <0x10000 0x10000>;
+                       interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               sec_jr1: jr@20000 {
+                       compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                       reg        = <0x20000 0x10000>;
+                       interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               sec_jr2: jr@30000 {
+                       compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                       reg        = <0x30000 0x10000>;
+                       interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               sec_jr3: jr@40000 {
+                       compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                       reg        = <0x40000 0x10000>;
+                       interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+               };
+       };
+
        clockgen: clocking@1300000 {
                compatible = "fsl,ls2080a-clockgen";
                reg = <0 0x1300000 0 0xa0000>;

diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 86192cbb7f3d1b0529fde684dc523407be5050f7..be330c130f599c56942da15006a29e6008a908e4 100644 (file)
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -3,6 +3,7 @@
  * Freescale ls1021a SOC common device tree source
  *
  * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include "skeleton.dtsi"
@@ -144,6 +145,45 @@
                        big-endian;
                };
 
+               crypto: crypto@1700000 {
+                       compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+                       fsl,sec-era = <7>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg              = <0x1700000 0x100000>;
+                       ranges           = <0x0 0x1700000 0x100000>;
+                       interrupts       = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+
+                       sec_jr0: jr@10000 {
+                               compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                               reg = <0x10000 0x10000>;
+                               interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       sec_jr1: jr@20000 {
+                               compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                               reg = <0x20000 0x10000>;
+                               interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       sec_jr2: jr@30000 {
+                               compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                               reg = <0x30000 0x10000>;
+                               interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       sec_jr3: jr@40000 {
+                               compatible = "fsl,sec-v5.0-job-ring",
+                                    "fsl,sec-v4.0-job-ring";
+                               reg = <0x40000 0x10000>;
+                               interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+               };
+
                clockgen: clocking@1ee1000 {
                        #address-cells = <1>;
                        #size-cells = <1>;