x86: ivybridge: bd82x6x: Support FSP enabled configuration

Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif,
and enable the build for both FSP and non-FSP configurations.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index d7332ffeed6ad569728d917368733f79eab3ee00..9203219f31698ab6af8d87678bce0ef3bdee138f 100644 (file)
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -7,7 +7,6 @@
 ifdef CONFIG_HAVE_FSP
 obj-y += fsp_configs.o ivybridge.o
 else
-obj-y += bd82x6x.o
 obj-y += car.o
 obj-y += cpu.o
 obj-y += early_me.o
@@ -21,3 +20,4 @@ obj-y += report_platform.o
 obj-y += sata.o
 obj-y += sdram.o
 endif
+obj-y += bd82x6x.o

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 996707b7feeadb833f144562e364277c6ff5491f..9972b0ae7ffe8cfcc2ff2fa865a9ecdd0454d8c6 100644 (file)
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -22,6 +22,7 @@
 #define GPIO_BASE      0x48
 #define BIOS_CTRL      0xdc
 
+#ifndef CONFIG_HAVE_FSP
 static int pch_revision_id = -1;
 static int pch_type = -1;
 
@@ -170,6 +171,7 @@ static int bd82x6x_probe(struct udevice *dev)
 
        return 0;
 }
+#endif /* CONFIG_HAVE_FSP */
 
 static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
 {
@@ -247,6 +249,8 @@ U_BOOT_DRIVER(bd82x6x_drv) = {
        .name           = "bd82x6x",
        .id             = UCLASS_PCH,
        .of_match       = bd82x6x_ids,
+#ifndef CONFIG_HAVE_FSP
        .probe          = bd82x6x_probe,
+#endif
        .ops            = &bd82x6x_pch_ops,
 };