#########################################################################
LIST_5xxx=" \
- BC3450 cm1_qp1 cpci5200 EVAL5200 \
+ BC3450 cm5200 cpci5200 EVAL5200 \
fo300 icecube_5100 icecube_5200 lite5200b \
mcc200 mecp5200 motionpro o2dnt \
pf5200 PM520 TB5200 Total5100 \
smmaco4_config: unconfig
@$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200
-cm1_qp1_config: unconfig
- @ >include/config.h
- @[ -z "$(findstring cm1_qp1,$@)" ] || \
- { echo "... with 64 MByte SDRAM" ; \
- echo "... with 32 MByte Flash" ; \
- }
- @./mkconfig -a cm1_qp1 ppc mpc5xxx cm1_qp1
+cm5200_config: unconfig
+ @./mkconfig -a cm5200 ppc mpc5xxx cm5200
spieval_config: unconfig
@$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200
+++ /dev/null
-/*
- * (C) Copyright 2003-2007
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2004-2005
- * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#ifdef CONFIG_OF_FLAT_TREE
-#include <ft_build.h>
-#endif /* CONFIG_OF_FLAT_TREE */
-
-#include "fwupdate.h"
-
-#ifndef CFG_RAMBOOT
-/*
- * Helper function to initialize SDRAM controller.
- */
-static void sdram_start(int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
- hi_addr_bit;
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
- hi_addr_bit;
-
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
- hi_addr_bit;
-
- /* auto refresh, second time */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
- hi_addr_bit;
-
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
-
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
-}
-#endif /* CFG_RAMBOOT */
-
-/*
- * Initalize SDRAM - configure SDRAM controller, detect memory size.
- */
-long int initdram(int board_type)
-{
- ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
- ulong test1, test2;
-
- /* configure SDRAM start/end for detection */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
-
- sdram_start(0);
- test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else
- dramsize = test2;
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20))
- dramsize = 0;
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
- __builtin_ffs(dramsize >> 20) - 1;
- } else
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-#else /* CFG_RAMBOOT */
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
- if (dramsize >= 0x13)
- dramsize = (1 << (dramsize - 0x13)) << 20;
- else
- dramsize = 0;
-#endif /* CFG_RAMBOOT */
-
- /*
- * On MPC5200B we need to set the special configuration delay in the
- * DDR controller. Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of
- * the MPC5200B User's Manual.
- */
- *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
- __asm__ volatile ("sync");
-
- return dramsize;
-}
-
-
-int checkboard(void)
-{
- puts("Board: CM1.QP1\n");
- return 0;
-}
-
-
-int board_early_init_r(void)
-{
- /*
- * Now, when we are in RAM, enable flash write access for detection
- * process. Note that CS_BOOT cannot be cleared when executing in
- * flash.
- */
- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
- return 0;
-}
-
-
-#ifdef CONFIG_POST
-int post_hotkeys_pressed(void)
-{
- return 0;
-}
-#endif /* CONFIG_POST */
-
-
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
-void post_word_store(ulong a)
-{
- vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
- *save_addr = a;
-}
-
-
-ulong post_word_load(void)
-{
- vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
- return *save_addr;
-}
-#endif /* CONFIG_POST || CONFIG_LOGBUFFER */
-
-
-#ifdef CONFIG_MISC_INIT_R
-int misc_init_r(void)
-{
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
- uchar buf[6];
- char str[18];
-
- /* Read ethaddr from EEPROM */
- if (i2c_read(CFG_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) {
- sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X",
- buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
- /* Check if MAC addr is owned by Schindler */
- if (strstr(str, "00:06:C3") != str) {
- printf(LOG_PREFIX "Warning - Illegal MAC address (%s)"
- " in EEPROM.\n", str);
- printf(LOG_PREFIX "Using MAC from environment\n");
- } else {
- printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n",
- str);
- setenv("ethaddr", str);
- }
- } else {
- printf(LOG_PREFIX "Warning - Unable to read MAC from I2C"
- " device at address %02X:%04X\n", CFG_I2C_EEPROM,
- CONFIG_MAC_OFFSET);
- printf(LOG_PREFIX "Using MAC from environment\n");
- }
- return 0;
-#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */
-}
-#endif /* CONFIG_MISC_INIT_R */
-
-
-#ifdef CONFIG_LAST_STAGE_INIT
-int last_stage_init(void)
-{
-#ifdef CONFIG_USB_STORAGE
- cm1_fwupdate();
-#endif /* CONFIG_USB_STORAGE */
- return 0;
-}
-#endif /* CONFIG_LAST_STAGE_INIT */
-
-
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-}
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o cmd_cm1_qp1.o fwupdate.o
+COBJS := $(BOARD).o cmd_cm5200.o fwupdate.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
--- /dev/null
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * Adapted to U-Boot 1.2 by:
+ * Bartlomiej Sieka <tur@semihalf.com>:
+ * - HW ID readout from EEPROM
+ * - module detection
+ * Grzegorz Bernacki <gjb@semihalf.com>:
+ * - run-time SDRAM controller configuration
+ * - LIBFDT support
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#ifdef CONFIG_OF_LIBFDT
+#include <libfdt.h>
+#include <libfdt_env.h>
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
+
+#include "cm5200.h"
+#include "fwupdate.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static hw_id_t hw_id;
+
+
+#ifndef CFG_RAMBOOT
+/*
+ * Helper function to initialize SDRAM controller.
+ */
+static void sdram_start(int hi_addr, mem_conf_t *mem_conf)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000000 |
+ hi_addr_bit;
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000002 |
+ hi_addr_bit;
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
+ hi_addr_bit;
+
+ /* auto refresh, second time */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
+ hi_addr_bit;
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = mem_conf->mode;
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit;
+}
+#endif /* CFG_RAMBOOT */
+
+
+/*
+ * Retrieve memory configuration for a given module. board_type is the index
+ * in hw_id_list[] corresponding to the module we are executing on; we return
+ * SDRAM controller settings approprate for this module.
+ */
+static mem_conf_t* get_mem_config(int board_type)
+{
+ switch(board_type){
+ case CM1_QA:
+ return memory_config[0];
+ case CM11_QA:
+ case CMU1_QA:
+ return memory_config[1];
+ default:
+ printf("ERROR: Unknown module, using a default SDRAM "
+ "configuration - things may not work!!!.\n");
+ return memory_config[0];
+ }
+}
+
+
+/*
+ * Initalize SDRAM - configure SDRAM controller, detect memory size.
+ */
+long int initdram(int board_type)
+{
+ ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+ ulong test1, test2;
+ mem_conf_t *mem_conf;
+
+ mem_conf = get_mem_config(board_type);
+
+ /* configure SDRAM start/end for detection */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = mem_conf->config1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2;
+
+ sdram_start(0, mem_conf);
+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+ sdram_start(1, mem_conf);
+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0, mem_conf);
+ dramsize = test1;
+ } else
+ dramsize = test2;
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+ __builtin_ffs(dramsize >> 20) - 1;
+ } else
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+#else /* CFG_RAMBOOT */
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13)
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ else
+ dramsize = 0;
+#endif /* !CFG_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of
+ * the MPC5200B User's Manual.
+ */
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+
+ return dramsize;
+}
+
+
+/*
+ * Read module hardware identification data from the I2C EEPROM.
+ */
+static void read_hw_id(hw_id_t hw_id)
+{
+ int i;
+ for (i = 0; i < HW_ID_ELEM_COUNT; ++i)
+ if (i2c_read(CFG_I2C_EEPROM,
+ hw_id_format[i].offset,
+ 2,
+ (uchar *)&hw_id[i][0],
+ hw_id_format[i].length) != 0)
+ printf("ERROR: can't read HW ID from EEPROM\n");
+}
+
+
+/*
+ * Identify module we are running on, set gd->board_type to the index in
+ * hw_id_list[] corresponding to the module identifed, or to
+ * CM5200_UNKNOWN_MODULE if we can't identify the module.
+ */
+static void identify_module(hw_id_t hw_id)
+{
+ int i, j, element;
+ char match;
+ gd->board_type = CM5200_UNKNOWN_MODULE;
+ for (i = 0; i < sizeof (hw_id_list) / sizeof (char **); ++i) {
+ match = 1;
+ for (j = 0; j < sizeof (hw_id_identify) / sizeof (int); ++j) {
+ element = hw_id_identify[j];
+ if (strncmp(hw_id_list[i][element],
+ &hw_id[element][0],
+ hw_id_format[element].length) != 0) {
+ match = 0;
+ break;
+ }
+ }
+ if (match) {
+ gd->board_type = i;
+ break;
+ }
+ }
+}
+
+
+/*
+ * Compose string with module name.
+ * buf is assumed to have enough space, and be null-terminated.
+ */
+static void compose_module_name(hw_id_t hw_id, char *buf)
+{
+ char tmp[MODULE_NAME_MAXLEN];
+ strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
+ strncat(buf, ".", 1);
+ strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
+ strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
+ strncat(buf, " (", 2);
+ strncat(buf, &hw_id[IDENTIFICATION_NUMBER][0],
+ hw_id_format[IDENTIFICATION_NUMBER].length);
+ sprintf(tmp, " / %u.%u)",
+ hw_id[MAJOR_SW_VERSION][0],
+ hw_id[MINOR_SW_VERSION][0]);
+ strcat(buf, tmp);
+}
+
+
+/*
+ * Compose string with hostname.
+ * buf is assumed to have enough space, and be null-terminated.
+ */
+static void compose_hostname(hw_id_t hw_id, char *buf)
+{
+ char *p;
+ strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
+ strncat(buf, "_", 1);
+ strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
+ strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
+ for (p = buf; *p; ++p)
+ *p = tolower(*p);
+
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+/*
+ * Update 'model' and 'memory' properties in the blob according to the module
+ * that we are running on.
+ */
+static void ft_blob_update(void *blob, bd_t *bd)
+{
+ int len, ret, nodeoffset = 0;
+ char module_name[MODULE_NAME_MAXLEN] = {0};
+ ulong memory_data[2] = {0};
+
+ compose_module_name(hw_id, module_name);
+ len = strlen(module_name) + 1;
+
+ ret = fdt_setprop(blob, nodeoffset, "model", module_name, len);
+ if (ret < 0)
+ printf("ft_blob_update(): cannot set /model property err:%s\n",
+ fdt_strerror(ret));
+
+ memory_data[0] = cpu_to_be32(bd->bi_memstart);
+ memory_data[1] = cpu_to_be32(bd->bi_memsize);
+
+ nodeoffset = fdt_find_node_by_path (blob, "/memory");
+ if (nodeoffset >= 0) {
+ ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
+ sizeof(memory_data));
+ if (ret < 0)
+ printf("ft_blob_update): cannot set /memory/reg "
+ "property err:%s\n", fdt_strerror(ret));
+ }
+ else {
+ /* memory node is required in dts */
+ printf("ft_blob_update(): cannot find /memory node "
+ "err:%s\n", fdt_strerror(nodeoffset));
+ }
+}
+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+
+
+/*
+ * Read HW ID from I2C EEPROM and detect the modue we are running on. Note
+ * that we need to use local variable for readout, because global data is not
+ * writable yet (and we'll have to redo the readout later on).
+ */
+int checkboard(void)
+{
+ hw_id_t hw_id_tmp;
+ char module_name_tmp[MODULE_NAME_MAXLEN] = "";
+
+ /*
+ * We need I2C to access HW ID data from EEPROM, so we call i2c_init()
+ * here despite the fact that it will be called again later on. We
+ * also use a little trick to silence I2C-related output.
+ */
+ gd->flags |= GD_FLG_SILENT;
+ i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ gd->flags &= ~GD_FLG_SILENT;
+
+ read_hw_id(hw_id_tmp);
+ identify_module(hw_id_tmp); /* this sets gd->board_type */
+ compose_module_name(hw_id_tmp, module_name_tmp);
+
+ if (gd->board_type != CM5200_UNKNOWN_MODULE)
+ printf("Board: %s\n", module_name_tmp);
+ else
+ printf("Board: unrecognized cm5200 module (%s)\n",
+ module_name_tmp);
+
+ return 0;
+}
+
+
+int board_early_init_r(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write access for detection
+ * process. Note that CS_BOOT cannot be cleared when executing in
+ * flash.
+ */
+ *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+
+ /* Now that we can write to global data, read HW ID again. */
+ read_hw_id(hw_id);
+ return 0;
+}
+
+
+#ifdef CONFIG_POST
+int post_hotkeys_pressed(void)
+{
+ return 0;
+}
+#endif /* CONFIG_POST */
+
+
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+void post_word_store(ulong a)
+{
+ vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
+ *save_addr = a;
+}
+
+
+ulong post_word_load(void)
+{
+ vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
+ return *save_addr;
+}
+#endif /* CONFIG_POST || CONFIG_LOGBUFFER */
+
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+ uchar buf[6];
+ char str[18];
+ char hostname[MODULE_NAME_MAXLEN];
+
+ /* Read ethaddr from EEPROM */
+ if (i2c_read(CFG_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) {
+ sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X",
+ buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ /* Check if MAC addr is owned by Schindler */
+ if (strstr(str, "00:06:C3") != str)
+ printf(LOG_PREFIX "Warning - Illegal MAC address (%s)"
+ " in EEPROM.\n", str);
+ else {
+ printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n",
+ str);
+ setenv("ethaddr", str);
+ }
+ } else {
+ printf(LOG_PREFIX "Warning - Unable to read MAC from I2C"
+ " device at address %02X:%04X\n", CFG_I2C_EEPROM,
+ CONFIG_MAC_OFFSET);
+ }
+#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */
+ if (!getenv("ethaddr"))
+ printf(LOG_PREFIX "MAC address not set, networking is not "
+ "operational\n");
+
+ /* set the hostname appropriate to the module we're running on */
+ compose_hostname(hw_id, hostname);
+ setenv("hostname", hostname);
+
+ return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+
+#ifdef CONFIG_LAST_STAGE_INIT
+int last_stage_init(void)
+{
+#ifdef CONFIG_USB_STORAGE
+ cm5200_fwupdate();
+#endif /* CONFIG_USB_STORAGE */
+ return 0;
+}
+#endif /* CONFIG_LAST_STAGE_INIT */
+
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ ft_blob_update(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
--- /dev/null
+/*
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * Author: Bartlomiej Sieka <tur@semihalf.com>
+ * Author: Grzegorz Bernacki <gjb@semihalf.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CM5200_H
+#define _CM5200_H
+
+
+/*
+ * Definitions and declarations for the modules of the cm5200 platform. Mostly
+ * related to reading the hardware identification data (HW ID) from the I2C
+ * EEPROM, detection of the particular module we are executing on, and
+ * appropriate SDRAM controller initialization.
+ */
+
+
+#define CM5200_UNKNOWN_MODULE 0xffffffff
+
+enum {
+ DEVICE_NAME, /* 0 */
+ GENERATION, /* 1 */
+ PCB_NAME, /* 2 */
+ FORM, /* 3 */
+ VERSION, /* 4 */
+ IDENTIFICATION_NUMBER, /* 5 */
+ MAJOR_SW_VERSION, /* 6 */
+ MINOR_SW_VERSION, /* 7 */
+ /* add new alements above this line */
+ HW_ID_ELEM_COUNT /* count */
+};
+
+/*
+ * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition"
+ */
+
+#define DEVICE_NAME_OFFSET 0x02
+#define GENERATION_OFFSET 0x0b
+#define PCB_NAME_OFFSET 0x0c
+#define FORM_OFFSET 0x15
+#define VERSION_OFFSET 0x16
+#define IDENTIFICATION_NUMBER_OFFSET 0x19
+#define MAJOR_SW_VERSION_OFFSET 0x0480
+#define MINOR_SW_VERSION_OFFSET 0x0481
+
+
+#define DEVICE_NAME_LEN 0x09
+#define GENERATION_LEN 0x01
+#define PCB_NAME_LEN 0x09
+#define FORM_LEN 0x01
+#define VERSION_LEN 0x03
+#define IDENTIFICATION_NUMBER_LEN 0x09
+#define MAJOR_SW_VERSION_LEN 0x01
+#define MINOR_SW_VERSION_LEN 0x01
+
+#define HW_ID_ELEM_MAXLEN 0x09 /* MAX(XXX_LEN) */
+
+/* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */
+#define MODULE_NAME_MAXLEN 64
+
+
+/* storage for HW ID read from EEPROM */
+typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN];
+
+
+/* HW ID layout in EEPROM */
+static struct {
+ unsigned int offset;
+ unsigned int length;
+} hw_id_format[HW_ID_ELEM_COUNT] = {
+ {DEVICE_NAME_OFFSET, DEVICE_NAME_LEN},
+ {GENERATION_OFFSET, GENERATION_LEN},
+ {PCB_NAME_OFFSET, PCB_NAME_LEN},
+ {FORM_OFFSET, FORM_LEN},
+ {VERSION_OFFSET, VERSION_LEN},
+ {IDENTIFICATION_NUMBER_OFFSET, IDENTIFICATION_NUMBER_LEN},
+ {MAJOR_SW_VERSION_OFFSET, MAJOR_SW_VERSION_LEN},
+ {MINOR_SW_VERSION_OFFSET, MINOR_SW_VERSION_LEN},
+};
+
+
+/* HW ID data found in EEPROM on supported modules */
+static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = {
+ "CM", /* DEVICE_NAME */
+ "1", /* GENERATION */
+ "CM1", /* PCB_NAME */
+ "Q", /* FORM */
+ "A", /* VERSION */
+ "591881", /* IDENTIFICATION_NUMBER */
+ "", /* MAJOR_SW_VERSION */
+ "", /* MINOR_SW_VERSION */
+};
+
+static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = {
+ "CM", /* DEVICE_NAME */
+ "1", /* GENERATION */
+ "CM11", /* PCB_NAME */
+ "Q", /* FORM */
+ "A", /* VERSION */
+ "594200", /* IDENTIFICATION_NUMBER */
+ "", /* MAJOR_SW_VERSION */
+ "", /* MINOR_SW_VERSION */
+};
+
+static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = {
+ "CMU", /* DEVICE_NAME */
+ "1", /* GENERATION */
+ "CMU1", /* PCB_NAME */
+ "Q", /* FORM */
+ "A", /* VERSION */
+ "594128", /* IDENTIFICATION_NUMBER */
+ "", /* MAJOR_SW_VERSION */
+ "", /* MINOR_SW_VERSION */
+};
+
+
+/* list of known modules */
+static char **hw_id_list[] = {
+ cm1_qa_hw_id,
+ cm11_qa_hw_id,
+ cmu1_qa_hw_id,
+};
+
+/* indices to the above list - keep in sync */
+enum {
+ CM1_QA,
+ CM11_QA,
+ CMU1_QA,
+};
+
+
+/* identify modules based on these hw id elements */
+static int hw_id_identify[] = {
+ PCB_NAME,
+ FORM,
+ VERSION,
+};
+
+
+/* Registers' settings for SDRAM controller intialization */
+typedef struct {
+ ulong mode;
+ ulong control;
+ ulong config1;
+ ulong config2;
+} mem_conf_t;
+
+static mem_conf_t k4s561632E = {
+ 0x00CD0000, /* CASL 3, burst length 8 */
+ 0x514F0000,
+ 0xE2333900,
+ 0x8EE70000
+};
+
+static mem_conf_t mt48lc32m16a2 = {
+ 0x00CD0000, /* CASL 3, burst length 8 */
+ 0x514F0000,
+ 0xD2322800,
+ 0x8AD70000
+};
+
+static mem_conf_t* memory_config[] = {
+ &k4s561632E,
+ &mt48lc32m16a2
+};
+
+#endif /* _CM5200_H */
/*
- * (C) Copyright 2007 Markus Kappeler <markus.kappeler@objectxp.com>
+ * (C) Copyright 2007 Markus Kappeler <markus.kappeler@objectxp.com>
+ *
+ * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>
*
* See file CREDITS for list of people who contributed to this
* project.
/*
* (C) Copyright 2007 Schindler Lift Inc.
- * (C) Copyright 2007 Semihalf
+ * (C) Copyright 2007 DENX Software Engineering
*
* Author: Michel Marti <mma@objectxp.com>
* Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>:
- * - code clean-up
- * - bugfix for overwriting bootargs by user
+ * - code clean-up
+ * - bugfix for overwriting bootargs by user
*
* See file CREDITS for list of people who contributed to this
* project.
static int load_rescue_image(ulong);
-void cm1_fwupdate(void)
+void cm5200_fwupdate(void)
{
cmd_tbl_t *bcmd;
char *rsargs;
if (do_fat_read(fwdir, NULL, 0, LS_NO) == -1) {
FW_DEBUG("No NX rescue image on "
"partition %d.\n", i);
+ partno = -2;
} else {
partno = i;
FW_DEBUG("Partition %d contains "
}
}
- if (partno == -1) {
- printf(LOG_PREFIX "Error: No valid (FAT) partition detected\n");
+ if (partno < 0) {
+ switch (partno) {
+ case -1:
+ printf(LOG_PREFIX "Error: No valid (FAT) partition "
+ "detected\n");
+ break;
+ case -2:
+ printf(LOG_PREFIX "Error: No NX rescue image on FAT "
+ "partition\n");
+ break;
+ default:
+ printf(LOG_PREFIX "Error: Failed with code %d\n",
+ partno);
+ }
usb_stop();
return 1;
}
#define __FW_UPDATE_H
/* Default prefix for output messages */
-#define LOG_PREFIX "CM1: "
+#define LOG_PREFIX "CM5200:"
/* Extra debug macro */
#ifdef CONFIG_FWUPDATE_DEBUG
#define RS_BOOTARGS "ramdisk=8192K"
/* Main function for fwupdate */
-void cm1_fwupdate(void);
+void cm5200_fwupdate(void);
#endif /* __FW_UPDATE_H */
fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
#if defined(CONFIG_CANMB) || \
- defined(CONFIG_CM1_QP1) || \
+ defined(CONFIG_CM5200) || \
defined(CONFIG_HMI1001) || \
defined(CONFIG_ICECUBE) || \
defined(CONFIG_INKA4X0) || \
*/
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
-#define CONFIG_CM1_QP1 1 /* ... on CM1.QP1 module */
+#define CONFIG_CM5200 1 /* ... on CM5200 platform */
/*
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */
/*
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "hostname=cm1_qp1\0" \
"netmask=255.255.0.0\0" \
"ipaddr=192.168.160.33\0" \
"serverip=192.168.1.1\0" \
"fdt_addr_flash=fc0a0000\0" \
"ramdisk_addr=500000\0" \
"rootpath=/opt/eldk-4.1/ppc_6xx\0" \
- "u-boot=/tftpboot/cm1_qp1/u-boot.bin\0" \
- "bootfile=/tftpboot/cm1_qp1/uImage\0" \
- "fdt_file=/tftpboot/cm1_qp1/cm1_qp1.dtb\0" \
+ "u-boot=/tftpboot/cm5200/u-boot.bin\0" \
+ "bootfile_fdt=/tftpboot/cm5200/uImage\0" \
+ "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \
"load=tftp ${u-boot_addr} ${u-boot}\0" \
- "update=prot off fc000000 fc05ffff; era fc000000 fc05ffff; " \
+ "update=prot off fc000000 +${filesize}; " \
+ "era fc000000 +${filesize}; " \
"cp.b ${u-boot_addr} fc000000 ${filesize}; " \
- "prot on fc000000 fc05ffff\0" \
+ "prot on fc000000 +${filesize}\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \
#define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CONFIG_BOARD_TYPES 1 /* we use board_type */
+
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#define CFG_FLASH_BASE 0xfc000000
+/* we need these despite using CFI */
+#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
+#define CFG_FLASH_SIZE 0x02000000 /* 32 MiB */
+
+
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT 1
+#undef CFG_LOWBOOT
#endif
#define SDRAM_CONFIG2 0x8EE70000
-/*
- * Flash configuration
- */
-#define CFG_FLASH_CFI 1
-#define CFG_FLASH_CFI_DRIVER 1
-#define CFG_FLASH_BASE TEXT_BASE
-/* we need these despite using CFI */
-#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
-#define CFG_FLASH_SIZE 0x02000000 /* 32 MiB */
-
/*
* MTD configuration
*/
#define CONFIG_JFFS2_CMDLINE 1
-#define MTDIDS_DEFAULT "nor0=cm1qp1-0"
-#define MTDPARTS_DEFAULT "mtdparts=cm1qp1-0:" \
+#define MTDIDS_DEFAULT "nor0=cm5200-0"
+#define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \
"384k(uboot),128k(env)," \
"128k(redund_env),128k(dtb)," \
"2m(kernel),27904k(rootfs)," \
/*
* Flat Device Tree support
*/
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-#define OF_FLAT_TREE_MAX_SIZE 8192 /* max size of the flat tree (8K) */
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
projects / u-boot.git / commitdiff