armv8/ls1043ardb: fix the limitation of using 'cpld reset'

The current 'cpld reset' will just write global_rst register
but couldn't switch to NOR boot if the board's switches are
for NAND/SD boot. So need to write rcw source registers for
NOR boot as well.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c
index 78c28246a823d1ce4935e8e7757c78fb6f426c56..c6452830edb9e495461bc913612fa24add89f0fc 100644 (file)
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -28,10 +28,18 @@ void cpld_write(unsigned int reg, u8 value)
 /* Set the boot bank to the alternate bank */
 void cpld_set_altbank(void)
 {
+       u16 reg = CPLD_CFG_RCW_SRC_NOR;
        u8 reg4 = CPLD_READ(soft_mux_on);
+       u8 reg5 = (u8)(reg >> 1);
+       u8 reg6 = (u8)(reg & 1);
        u8 reg7 = CPLD_READ(vbank);
 
-       CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
+       cpld_rev_bit(&reg5);
+
+       CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+       CPLD_WRITE(cfg_rcw_src1, reg5);
+       CPLD_WRITE(cfg_rcw_src2, reg6);
 
        reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
        CPLD_WRITE(vbank, reg7);
@@ -42,7 +50,21 @@ void cpld_set_altbank(void)
 /* Set the boot bank to the default bank */
 void cpld_set_defbank(void)
 {
-       CPLD_WRITE(global_rst, 1);
+       u16 reg = CPLD_CFG_RCW_SRC_NOR;
+       u8 reg4 = CPLD_READ(soft_mux_on);
+       u8 reg5 = (u8)(reg >> 1);
+       u8 reg6 = (u8)(reg & 1);
+
+       cpld_rev_bit(&reg5);
+
+       CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+       CPLD_WRITE(cfg_rcw_src1, reg5);
+       CPLD_WRITE(cfg_rcw_src2, reg6);
+
+       CPLD_WRITE(vbank, 0);
+
+       CPLD_WRITE(system_rst, 1);
 }
 
 void cpld_set_nand(void)

diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h
index bd59c0e5d58e19c6d24eee72f92d0e0d74862d46..cb175b56fa4ae8f13bc82ecac6abbc9629f07247 100644 (file)
--- a/board/freescale/ls1043ardb/cpld.h
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value);
 #define CPLD_SW_MUX_BANK_SEL   0x40
 #define CPLD_BANK_SEL_MASK     0x07
 #define CPLD_BANK_SEL_ALTBANK  0x04
+#define CPLD_CFG_RCW_SRC_NOR   0x025
 #define CPLD_CFG_RCW_SRC_NAND  0x106
 #define CPLD_CFG_RCW_SRC_SD    0x040
 #endif