Move the bus initialization code to this driver from board files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
#include "micro-support-card.h"
#include "soc-info.h"
+#define PC0CTRL 0x598000c0
+
+#if defined(CONFIG_ARCH_UNIPHIER_LD4) || defined(CONFIG_ARCH_UNIPHIER_SLD8)
+static void uniphier_ld4_sbc_init(void)
+{
+ u32 tmp;
+
+ /* system bus output enable */
+ tmp = readl(PC0CTRL);
+ tmp &= 0xfffffcff;
+ writel(tmp, PC0CTRL);
+}
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || \
+ defined(CONFIG_ARCH_UNIPHIER_LD6B) || \
+ defined(CONFIG_ARCH_UNIPHIER_LD11) || \
+ defined(CONFIG_ARCH_UNIPHIER_LD20) || \
+ defined(CONFIG_ARCH_UNIPHIER_PXS3)
+static void uniphier_pxs2_sbc_init(void)
+{
+ /* necessary for ROM boot ?? */
+ /* system bus output enable */
+ writel(0x17, PC0CTRL);
+}
+#endif
+
#ifdef CONFIG_ARCH_UNIPHIER_LD20
static void uniphier_ld20_misc_init(void)
{
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
{
.soc_id = UNIPHIER_PRO4_ID,
- .sbc_init = uniphier_sbc_init_savepin,
.pll_init = uniphier_pro4_pll_init,
.clk_init = uniphier_pro4_clk_init,
},
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
{
.soc_id = UNIPHIER_PRO5_ID,
- .sbc_init = uniphier_sbc_init_savepin,
.clk_init = uniphier_pro5_clk_init,
},
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD11)
{
.soc_id = UNIPHIER_LD11_ID,
- .sbc_init = uniphier_ld11_sbc_init,
+ .sbc_init = uniphier_pxs2_sbc_init,
.pll_init = uniphier_ld11_pll_init,
.clk_init = uniphier_ld11_clk_init,
},
#if defined(CONFIG_ARCH_UNIPHIER_LD20)
{
.soc_id = UNIPHIER_LD20_ID,
- .sbc_init = uniphier_ld11_sbc_init,
+ .sbc_init = uniphier_pxs2_sbc_init,
.pll_init = uniphier_ld20_pll_init,
.clk_init = uniphier_ld20_clk_init,
.misc_init = uniphier_ld20_misc_init,
return -EINVAL;
}
- initdata->sbc_init();
+ if (initdata->sbc_init)
+ initdata->sbc_init();
support_card_init();
int uniphier_pro5_init(const struct uniphier_board_data *bd);
int uniphier_pxs2_init(const struct uniphier_board_data *bd);
-#if defined(CONFIG_MICRO_SUPPORT_CARD)
-void uniphier_sbc_init_savepin(void);
-void uniphier_ld4_sbc_init(void);
-void uniphier_pxs2_sbc_init(void);
-void uniphier_ld11_sbc_init(void);
-#else
-static inline void uniphier_sbc_init_savepin(void)
-{
-}
-
-static inline void uniphier_ld4_sbc_init(void)
-{
-}
-
-static inline void uniphier_pxs2_sbc_init(void)
-{
-}
-
-static inline void uniphier_ld11_sbc_init(void)
-{
-}
-#endif
-
void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd);
int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd);
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
-#include <dm/of.h>
+#include <dm.h>
#include <fdt_support.h>
#include <linux/ctype.h>
#include <linux/delay.h>
void support_card_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ /* The system bus must be initialized for access to the support card. */
+ ret = uclass_get_device_by_driver(UCLASS_SIMPLE_BUS,
+ DM_GET_DRIVER(uniphier_system_bus_driver),
+ &dev);
+ if (ret)
+ return;
+
+ /* Check DT to see if this board has the support card. */
support_card_detect();
if (!support_card_found)
# SPDX-License-Identifier: GPL-2.0+
obj-y += sbc-boot.o
-
-ifndef CONFIG_SPL_BUILD
-ifdef CONFIG_MICRO_SUPPORT_CARD
-obj-y += sbc.o
-
-obj-$(CONFIG_ARCH_UNIPHIER_LD4) += sbc-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD11) += sbc-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-ld11.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += sbc-pxs2.o
-endif
-endif
#include <linux/io.h>
-#include "sbc-regs.h"
+#define SBBASE0 0x58c00100
+#define SBBASE_BANK_ENABLE (0x00000001)
int uniphier_sbc_boot_is_swapped(void)
{
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016-2017 Socionext Inc.
- */
-
-#include <spl.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "sbc-regs.h"
-
-void uniphier_ld11_sbc_init(void)
-{
- if (!uniphier_sbc_is_enabled())
- return;
-
- uniphier_sbc_init_savepin();
-
- /* necessary for ROM boot ?? */
- /* system bus output enable */
- writel(0x17, PC0CTRL);
-
- /* pins for NAND and System Bus are multiplexed */
- if (spl_boot_device() != BOOT_DEVICE_NAND)
- uniphier_pin_init("system-bus");
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- * Copyright (C) 2015-2017 Socionext Inc.
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "sbc-regs.h"
-
-void uniphier_ld4_sbc_init(void)
-{
- u32 tmp;
-
- if (!uniphier_sbc_is_enabled())
- return;
-
- uniphier_sbc_init_savepin();
-
- /* system bus output enable */
- tmp = readl(PC0CTRL);
- tmp &= 0xfffffcff;
- writel(tmp, PC0CTRL);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016-2017 Socionext Inc.
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "sbc-regs.h"
-
-void uniphier_pxs2_sbc_init(void)
-{
- if (!uniphier_sbc_is_enabled())
- return;
-
- uniphier_sbc_init_savepin();
-
- /* necessary for ROM boot ?? */
- /* system bus output enable */
- writel(0x17, PC0CTRL);
-
- uniphier_pin_init("system-bus"); /* PXs3 */
-}
#ifndef ARCH_SBC_REGS_H
#define ARCH_SBC_REGS_H
-#define SBBASE_BASE 0x58c00100
-#define SBBASE(x) (SBBASE_BASE + (x) * 0x10)
-
-#define SBBASE0 (SBBASE(0))
-#define SBBASE1 (SBBASE(1))
-#define SBBASE2 (SBBASE(2))
-#define SBBASE3 (SBBASE(3))
-#define SBBASE4 (SBBASE(4))
-#define SBBASE5 (SBBASE(5))
-#define SBBASE6 (SBBASE(6))
-#define SBBASE7 (SBBASE(7))
-
-#define SBBASE_BANK_ENABLE (0x00000001)
-
-#define SBCTRL_BASE 0x58c00200
-#define SBCTRL(x, y) (SBCTRL_BASE + (x) * 0x10 + (y) * 4)
-
-#define SBCTRL00 SBCTRL(0, 0)
-#define SBCTRL01 SBCTRL(0, 1)
-#define SBCTRL02 SBCTRL(0, 2)
-#define SBCTRL03 SBCTRL(0, 3)
-#define SBCTRL04 (SBCTRL_BASE + 0x100)
-
-#define SBCTRL10 SBCTRL(1, 0)
-#define SBCTRL11 SBCTRL(1, 1)
-#define SBCTRL12 SBCTRL(1, 2)
-#define SBCTRL13 SBCTRL(1, 3)
-#define SBCTRL14 (SBCTRL_BASE + 0x110)
-
-#define SBCTRL20 SBCTRL(2, 0)
-#define SBCTRL21 SBCTRL(2, 1)
-#define SBCTRL22 SBCTRL(2, 2)
-#define SBCTRL23 SBCTRL(2, 3)
-#define SBCTRL24 (SBCTRL_BASE + 0x120)
-
-#define SBCTRL30 SBCTRL(3, 0)
-#define SBCTRL31 SBCTRL(3, 1)
-#define SBCTRL32 SBCTRL(3, 2)
-#define SBCTRL33 SBCTRL(3, 3)
-#define SBCTRL34 (SBCTRL_BASE + 0x130)
-
-#define SBCTRL40 SBCTRL(4, 0)
-#define SBCTRL41 SBCTRL(4, 1)
-#define SBCTRL42 SBCTRL(4, 2)
-#define SBCTRL43 SBCTRL(4, 3)
-#define SBCTRL44 (SBCTRL_BASE + 0x140)
-
-#define SBCTRL50 SBCTRL(5, 0)
-#define SBCTRL51 SBCTRL(5, 1)
-#define SBCTRL52 SBCTRL(5, 2)
-#define SBCTRL53 SBCTRL(5, 3)
-#define SBCTRL54 (SBCTRL_BASE + 0x150)
-
-#define SBCTRL60 SBCTRL(6, 0)
-#define SBCTRL61 SBCTRL(6, 1)
-#define SBCTRL62 SBCTRL(6, 2)
-#define SBCTRL63 SBCTRL(6, 3)
-#define SBCTRL64 (SBCTRL_BASE + 0x160)
-
-#define SBCTRL70 SBCTRL(7, 0)
-#define SBCTRL71 SBCTRL(7, 1)
-#define SBCTRL72 SBCTRL(7, 2)
-#define SBCTRL73 SBCTRL(7, 3)
-#define SBCTRL74 (SBCTRL_BASE + 0x170)
-
-#define PC0CTRL 0x598000c0
-
int uniphier_sbc_boot_is_swapped(void);
-int uniphier_sbc_is_enabled(void);
#endif /* ARCH_SBC_REGS_H */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- * Copyright (C) 2015-2017 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- */
-
-#include <linux/io.h>
-#include <asm/global_data.h>
-
-#include "../init.h"
-#include "sbc-regs.h"
-
-/* slower but LED works */
-#define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
-#define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
-#define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
-#define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
-
-/* faster but LED does not work */
-#define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
-#define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
-#define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
-#define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
-
-int uniphier_sbc_is_enabled(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
- const void *fdt = gd->fdt_blob;
- int offset;
-
- offset = fdt_node_offset_by_compatible(fdt, 0,
- "socionext,uniphier-system-bus");
- if (offset < 0)
- return 0;
-
- return fdtdec_get_is_enabled(fdt, offset);
-}
-
-void uniphier_sbc_init_savepin(void)
-{
- /*
- * Only CS1 is connected to support card.
- * BKSZ[1:0] should be set to "01".
- */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
-
- if (uniphier_sbc_boot_is_swapped()) {
- /*
- * Boot Swap On: boot from external NOR/SRAM
- * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
- *
- * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
- * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
- */
- writel(0x0000bc01, SBBASE0);
- } else {
- /*
- * Boot Swap Off: boot from mask ROM
- * 0x40000000-0x41ffffff: mask ROM
- * 0x42000000-0x43efffff: memory bank (31MB)
- * 0x43f00000-0x43ffffff: peripherals (1MB)
- */
- writel(0x0000be01, SBBASE0); /* dummy */
- writel(0x0200be01, SBBASE1);
- }
-}
// SPDX-License-Identifier: GPL-2.0-or-later
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <linux/types.h>
#include <dm.h>
+/* System Bus Controller registers */
+#define UNIPHIER_SBC_BASE 0x100 /* base address of bank0 space */
+#define UNIPHIER_SBC_BASE_BE BIT(0) /* bank_enable */
+#define UNIPHIER_SBC_CTRL0 0x200 /* timing parameter 0 of bank0 */
+#define UNIPHIER_SBC_CTRL1 0x204 /* timing parameter 1 of bank0 */
+#define UNIPHIER_SBC_CTRL2 0x208 /* timing parameter 2 of bank0 */
+#define UNIPHIER_SBC_CTRL3 0x20c /* timing parameter 3 of bank0 */
+#define UNIPHIER_SBC_CTRL4 0x300 /* timing parameter 4 of bank0 */
+
+#define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */
+
+#if 1
+/* slower but LED works */
+#define SBCTRL0_VALUE 0x55450000
+#define SBCTRL1_VALUE 0x07168d00
+#define SBCTRL2_VALUE 0x34000009
+#define SBCTRL4_VALUE 0x02110110
+
+#else
+/* faster but LED does not work */
+#define SBCTRL0_VALUE 0x55450000
+#define SBCTRL1_VALUE 0x06057700
+/* NOR flash needs more wait counts than SRAM */
+#define SBCTRL2_VALUE 0x34000009
+#define SBCTRL4_VALUE 0x02110210
+#endif
+
+void uniphier_system_bus_set_reg(void __iomem *membase)
+{
+ void __iomem *bank0_base = membase;
+ void __iomem *bank1_base = membase + UNIPHIER_SBC_STRIDE;
+
+ /*
+ * Only CS1 is connected to support card.
+ * BKSZ[1:0] should be set to "01".
+ */
+ writel(SBCTRL0_VALUE, bank1_base + UNIPHIER_SBC_CTRL0);
+ writel(SBCTRL1_VALUE, bank1_base + UNIPHIER_SBC_CTRL1);
+ writel(SBCTRL2_VALUE, bank1_base + UNIPHIER_SBC_CTRL2);
+ writel(SBCTRL4_VALUE, bank1_base + UNIPHIER_SBC_CTRL4);
+
+ if (readl(bank1_base + UNIPHIER_SBC_BASE) & UNIPHIER_SBC_BASE_BE) {
+ /*
+ * Boot Swap On: boot from external NOR/SRAM
+ * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
+ *
+ * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
+ * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
+ */
+ writel(0x0000bc01, bank0_base + UNIPHIER_SBC_BASE);
+ } else {
+ /*
+ * Boot Swap Off: boot from mask ROM
+ * 0x40000000-0x41ffffff: mask ROM
+ * 0x42000000-0x43efffff: memory bank (31MB)
+ * 0x43f00000-0x43ffffff: peripherals (1MB)
+ */
+ writel(0x0000be01, bank0_base + UNIPHIER_SBC_BASE); /* dummy */
+ writel(0x0200be01, bank0_base + UNIPHIER_SBC_BASE);
+ }
+}
+
+static int uniphier_system_bus_probe(struct udevice *dev)
+{
+ fdt_addr_t base;
+ void __iomem *membase;
+
+ base = dev_read_addr(dev);
+ if (base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ membase = devm_ioremap(dev, base, SZ_1K);
+ if (!membase)
+ return -ENOMEM;
+
+ uniphier_system_bus_set_reg(membase);
+
+ return 0;
+}
+
static const struct udevice_id uniphier_system_bus_match[] = {
{ .compatible = "socionext,uniphier-system-bus" },
{ /* sentinel */ }
.name = "uniphier-system-bus",
.id = UCLASS_SIMPLE_BUS,
.of_match = uniphier_system_bus_match,
+ .probe = uniphier_system_bus_probe,
};
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