mtd: cqspi: Wait for transfer completion

Wait for the read/write transfer finish bit get actually cleared,
this does not happen immediately on at least SoCFPGA Gen5.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Pratyush Yadav <p.yadav@ti.com>

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 429ee335db6ec948b19170d5f4f96da9aabd2922..2cdf4c9c9f8dc7387ef23d3a260926d97f3c8a7e 100644 (file)
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -858,6 +858,14 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat,
        writel(CQSPI_REG_INDIRECTRD_DONE,
               plat->regbase + CQSPI_REG_INDIRECTRD);
 
+       /* Check indirect done status */
+       ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
+                               CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0);
+       if (ret) {
+               printf("Indirect read clear completion error (%i)\n", ret);
+               goto failrd;
+       }
+
        return 0;
 
 failrd:
@@ -1012,6 +1020,15 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat,
        /* Clear indirect completion status */
        writel(CQSPI_REG_INDIRECTWR_DONE,
               plat->regbase + CQSPI_REG_INDIRECTWR);
+
+       /* Check indirect done status */
+       ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
+                               CQSPI_REG_INDIRECTWR_DONE, 0, 10, 0);
+       if (ret) {
+               printf("Indirect write clear completion error (%i)\n", ret);
+               goto failwr;
+       }
+
        if (bounce_buf)
                free(bounce_buf);
        return 0;