* drivers/gpu/drm/stm/dw_mipi_dsi-stm.c.
*/
+#define LOG_CATEGORY UCLASS_VIDEO_BRIDGE
+
#include <common.h>
#include <clk.h>
#include <dm.h>
case MIPI_DSI_FMT_RGB565:
return DSI_RGB565_CONF1;
default:
- pr_err("MIPI color invalid, so we use rgb888\n");
+ log_err("MIPI color invalid, so we use rgb888\n");
}
return DSI_RGB888;
}
u32 val;
int ret;
- debug("Initialize DSI physical layer\n");
+ dev_dbg(dev, "Initialize DSI physical layer\n");
/* Enable the regulator */
dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN);
ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
TIMEOUT_US);
if (ret) {
- debug("!TIMEOUT! waiting REGU\n");
+ dev_dbg(dev, "!TIMEOUT! waiting REGU\n");
return ret;
}
ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
TIMEOUT_US);
if (ret) {
- debug("!TIMEOUT! waiting PLL\n");
+ dev_dbg(dev, "!TIMEOUT! waiting PLL\n");
return ret;
}
struct udevice *dev = device->dev;
struct stm32_dsi_priv *dsi = dev_get_priv(dev);
- debug("Set mode %p enable %ld\n", dsi,
- mode_flags & MIPI_DSI_MODE_VIDEO);
+ dev_dbg(dev, "Set mode %p enable %ld\n", dsi,
+ mode_flags & MIPI_DSI_MODE_VIDEO);
if (!dsi)
return;
*lane_mbps = pll_out_khz / 1000;
- debug("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
- pll_in_khz, pll_out_khz, *lane_mbps);
+ dev_dbg(dev, "pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
+ pll_in_khz, pll_out_khz, *lane_mbps);
return 0;
}