sunxi: A64: do an RMR switch if started in AArch32 mode

The Allwinner A64 SoC starts execution in AArch32 mode, and both
the boot ROM and Allwinner's boot0 keep running in this mode.
So U-Boot gets entered in 32-bit, although we want it to run in AArch64.

By using a "magic" instruction, which happens to be an almost-NOP in
AArch64 and a branch in AArch32, we differentiate between being
entered in 64-bit or 32-bit mode.
If in 64-bit mode, we proceed with the branch to reset, but in 32-bit
mode we trigger an RMR write to bring the core into AArch64/EL3 and
re-enter U-Boot at CONFIG_SYS_TEXT_BASE.
This allows a 64-bit U-Boot to be both entered in 32 and 64-bit mode,
so we can use the same start code for the SPL and the U-Boot proper.

We use the existing custom header (boot0.h) functionality, but restrict
the existing boot0 header reservation to the non-SPL build now. A SPL
wouldn't need such header anyway. This allows to have both options
defined and lets us use one for the SPL and the other for U-Boot proper.

Also add arch/arm/mach-sunxi/rmr_switch.S, which contains the original
ARM assembly code and instructions how to re-generate the encoded
version.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
index 6a13db5222ab136a91a77333e3bdd7c695e85d92..9c6d82dda18e7604cb3788c7df4d223930e220b0 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -4,6 +4,36 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
+#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD)
 /* reserve space for BOOT0 header information */
        b       reset
        .space  1532
+#elif defined(CONFIG_ARM_BOOT_HOOK_RMR)
+/*
+ * Switch into AArch64 if needed.
+ * Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source.
+ */
+       tst     x0, x0                  // this is "b #0x84" in ARM
+       b       reset
+       .space  0x7c
+       .word   0xe59f1024      // ldr     r1, [pc, #36] ; 0x170000a0
+       .word   0xe59f0024      // ldr     r0, [pc, #36] ; CONFIG_*_TEXT_BASE
+       .word   0xe5810000      // str     r0, [r1]
+       .word   0xf57ff04f      // dsb     sy
+       .word   0xf57ff06f      // isb     sy
+       .word   0xee1c0f50      // mrc     15, 0, r0, cr12, cr0, {2} ; RMR
+       .word   0xe3800003      // orr     r0, r0, #3
+       .word   0xee0c0f50      // mcr     15, 0, r0, cr12, cr0, {2} ; RMR
+       .word   0xf57ff06f      // isb     sy
+       .word   0xe320f003      // wfi
+       .word   0xeafffffd      // b       @wfi
+       .word   0x017000a0      // writeable RVBAR mapping address
+#ifdef CONFIG_SPL_BUILD
+       .word   CONFIG_SPL_TEXT_BASE
+#else
+       .word   CONFIG_SYS_TEXT_BASE
+#endif
+#else
+/* normal execution */
+       b       reset
+#endif

diff --git a/arch/arm/mach-sunxi/rmr_switch.S b/arch/arm/mach-sunxi/rmr_switch.S
new file mode 100644 (file)
index 0000000..cefa930
--- /dev/null
+++ b/arch/arm/mach-sunxi/rmr_switch.S
@@ -0,0 +1,41 @@
+@
+@ ARMv8 RMR reset sequence on Allwinner SoCs.
+@
+@ All 64-bit capable Allwinner SoCs reset in AArch32 (and continue to
+@ exectute the Boot ROM in this state), so we need to switch to AArch64
+@ at some point.
+@ Section G6.2.133 of the ARMv8 ARM describes the Reset Management Register
+@ (RMR), which triggers a warm-reset of a core and can request to switch
+@ into a different execution state (AArch32 or AArch64).
+@ The address at which execution starts after the reset is held in the
+@ RVBAR system register, which is architecturally read-only.
+@ Allwinner provides a writable alias of this register in MMIO space, so
+@ we can easily set the start address of AArch64 code.
+@ This code below switches to AArch64 and starts execution at the specified
+@ start address. It needs to be assembled by an ARM(32) assembler and
+@ the machine code must be inserted as verbatim .word statements into the
+@ beginning of the AArch64 U-Boot code.
+@ To get the encoded bytes, use:
+@ ${CROSS_COMPILE}gcc -c -o rmr_switch.o rmr_switch.S
+@ ${CROSS_COMPILE}objdump -d rmr_switch.o
+@
+@ The resulting words should be inserted into the U-Boot file at
+@ arch/arm/include/asm/arch-sunxi/boot0.h.
+@
+@ This file is not build by the U-Boot build system, but provided only as a
+@ reference and to be able to regenerate a (probably fixed) version of this
+@ code found in encoded form in boot0.h.
+
+.text
+
+       ldr     r1, =0x017000a0         @ MMIO mapped RVBAR[0] register
+       ldr     r0, =0x57aA7add         @ start address, to be replaced
+       str     r0, [r1]
+       dsb     sy
+       isb     sy
+       mrc     15, 0, r0, cr12, cr0, 2 @ read RMR register
+       orr     r0, r0, #3              @ request reset in AArch64
+       mcr     15, 0, r0, cr12, cr0, 2 @ write RMR register
+       isb     sy
+1:     wfi
+       b       1b

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 0cd57a2d85fa3170338dd2b4285362ea0cd2c604..f02057386558aa90e2facb551cc0929d5a6795ac 100644 (file)
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -142,6 +142,20 @@ config RESERVE_ALLWINNER_BOOT0_HEADER
        blob relies on this information to load and execute U-Boot.
        Only needed on 64-bit Allwinner boards so far when using boot0.
 
+config ARM_BOOT_HOOK_RMR
+       bool
+       depends on ARM64
+       default y
+       select ENABLE_ARM_SOC_BOOT0_HOOK
+       ---help---
+       Insert some ARM32 code at the very beginning of the U-Boot binary
+       which uses an RMR register write to bring the core into AArch64 mode.
+       The very first instruction acts as a switch, since it's carefully
+       chosen to be a NOP in one mode and a branch in the other, so the
+       code would only be executed if not already in AArch64.
+       This allows both the SPL and the U-Boot proper to be entered in
+       either mode and switch to AArch64 if needed.
+
 config DRAM_TYPE
        int "sunxi dram type"
        depends on MACH_SUN8I_A83T