]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
board: sifive: use ccache driver instead of helper function
authorZong Li <zong.li@sifive.com>
Wed, 1 Sep 2021 07:01:42 +0000 (15:01 +0800)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Tue, 7 Sep 2021 02:34:29 +0000 (10:34 +0800)
Invokes the common cache_init function to initialize ccache.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
arch/riscv/cpu/fu540/Kconfig
arch/riscv/cpu/fu540/Makefile
arch/riscv/cpu/fu540/cache.c [deleted file]
arch/riscv/cpu/fu740/Kconfig
arch/riscv/cpu/fu740/Makefile
arch/riscv/cpu/fu740/cache.c [deleted file]
arch/riscv/include/asm/arch-fu540/cache.h [deleted file]
arch/riscv/include/asm/arch-fu740/cache.h [deleted file]
board/sifive/unleashed/unleashed.c
board/sifive/unmatched/unmatched.c

index 05463b26258624d138595d1b2b84e6c54c92d65b..1604b412b4865758d4ce208077e1d82b52567deb 100644 (file)
@@ -19,6 +19,8 @@ config SIFIVE_FU540
        imply SMP
        imply CLK_SIFIVE
        imply CLK_SIFIVE_PRCI
+       imply SIFIVE_CACHE
+       imply SIFIVE_CCACHE
        imply SIFIVE_SERIAL
        imply MACB
        imply MII
index 088205ef57e7698de573f3857397386a5ecb6d77..043fb961a51e99abfe6e8a976f9ee20cea74d6f0 100644 (file)
@@ -8,5 +8,4 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
-obj-y += cache.o
 endif
diff --git a/arch/riscv/cpu/fu540/cache.c b/arch/riscv/cpu/fu540/cache.c
deleted file mode 100644 (file)
index 0fc4ef6..0000000
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020 SiFive, Inc
- *
- * Authors:
- *   Pragnesh Patel <pragnesh.patel@sifive.com>
- */
-
-#include <common.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-
-/* Register offsets */
-#define L2_CACHE_CONFIG        0x000
-#define L2_CACHE_ENABLE        0x008
-
-#define MASK_NUM_WAYS  GENMASK(15, 8)
-#define NUM_WAYS_SHIFT 8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cache_enable_ways(void)
-{
-       const void *blob = gd->fdt_blob;
-       int node;
-       fdt_addr_t base;
-       u32 config;
-       u32 ways;
-
-       volatile u32 *enable;
-
-       node = fdt_node_offset_by_compatible(blob, -1,
-                                            "sifive,fu540-c000-ccache");
-
-       if (node < 0)
-               return node;
-
-       base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
-                                               NULL, false);
-       if (base == FDT_ADDR_T_NONE)
-               return FDT_ADDR_T_NONE;
-
-       config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
-       ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
-
-       enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
-
-       /* memory barrier */
-       mb();
-       (*enable) = ways - 1;
-       /* memory barrier */
-       mb();
-       return 0;
-}
index 408195f1497a5963e982b0670007d279ce04a25a..049a0a05841de2835b84797100a0a395f63061b8 100644 (file)
@@ -19,6 +19,8 @@ config SIFIVE_FU740
        imply SMP
        imply CLK_SIFIVE
        imply CLK_SIFIVE_PRCI
+       imply SIFIVE_CACHE
+       imply SIFIVE_CCACHE
        imply SIFIVE_SERIAL
        imply MACB
        imply MII
index 5ef8ac18a717cc23b8a27d22a2bd7f1437cd8d96..1d1ad98ba7c68a1d75226a2843bccc1c5e61d198 100644 (file)
@@ -8,5 +8,4 @@ obj-y += spl.o
 else
 obj-y += dram.o
 obj-y += cpu.o
-obj-y += cache.o
 endif
diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c
deleted file mode 100644 (file)
index 680955c..0000000
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020-2021 SiFive, Inc
- *
- * Authors:
- *   Pragnesh Patel <pragnesh.patel@sifive.com>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/bitops.h>
-#include <asm/global_data.h>
-
-/* Register offsets */
-#define L2_CACHE_CONFIG        0x000
-#define L2_CACHE_ENABLE        0x008
-
-#define MASK_NUM_WAYS  GENMASK(15, 8)
-#define NUM_WAYS_SHIFT 8
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int cache_enable_ways(void)
-{
-       const void *blob = gd->fdt_blob;
-       int node;
-       fdt_addr_t base;
-       u32 config;
-       u32 ways;
-
-       volatile u32 *enable;
-
-       node = fdt_node_offset_by_compatible(blob, -1,
-                                            "sifive,fu740-c000-ccache");
-
-       if (node < 0)
-               return node;
-
-       base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
-                                               NULL, false);
-       if (base == FDT_ADDR_T_NONE)
-               return FDT_ADDR_T_NONE;
-
-       config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
-       ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
-
-       enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
-
-       /* memory barrier */
-       mb();
-       (*enable) = ways - 1;
-       /* memory barrier */
-       mb();
-       return 0;
-}
diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h
deleted file mode 100644 (file)
index 135a17c..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2020 SiFive, Inc.
- *
- * Authors:
- *   Pragnesh Patel <pragnesh.patel@sifve.com>
- */
-
-#ifndef _CACHE_SIFIVE_H
-#define _CACHE_SIFIVE_H
-
-int cache_enable_ways(void);
-
-#endif /* _CACHE_SIFIVE_H */
diff --git a/arch/riscv/include/asm/arch-fu740/cache.h b/arch/riscv/include/asm/arch-fu740/cache.h
deleted file mode 100644 (file)
index 7d4fe99..0000000
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2020-2021 SiFive, Inc.
- *
- * Authors:
- *   Pragnesh Patel <pragnesh.patel@sifve.com>
- */
-
-#ifndef _CACHE_SIFIVE_H
-#define _CACHE_SIFIVE_H
-
-int cache_enable_ways(void);
-
-#endif /* _CACHE_SIFIVE_H */
index fa65fcade086fe64a21102f2a7744ce17613941b..8cd514df3005caedd4b926a92b0a08a39a373b8d 100644 (file)
@@ -6,6 +6,7 @@
  *   Anup Patel <anup.patel@wdc.com>
  */
 
+#include <cpu_func.h>
 #include <dm.h>
 #include <env.h>
 #include <init.h>
@@ -15,7 +16,6 @@
 #include <linux/delay.h>
 #include <misc.h>
 #include <spl.h>
-#include <asm/arch/cache.h>
 #include <asm/sections.h>
 
 /*
@@ -126,14 +126,8 @@ void *board_fdt_blob_setup(void)
 
 int board_init(void)
 {
-       int ret;
-
        /* enable all cache ways */
-       ret = cache_enable_ways();
-       if (ret) {
-               debug("%s: could not enable cache ways\n", __func__);
-               return ret;
-       }
+       enable_caches();
 
        return 0;
 }
index da23a6ce246cef61aead72f5227348bdbb496fe6..d90b252baef728b8a75fa6ba37eeb259e36a3ee2 100644 (file)
@@ -7,8 +7,8 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
 #include <dm.h>
-#include <asm/arch/cache.h>
 #include <asm/sections.h>
 
 void *board_fdt_blob_setup(void)
@@ -23,13 +23,8 @@ void *board_fdt_blob_setup(void)
 
 int board_init(void)
 {
-       int ret;
-
        /* enable all cache ways */
-       ret = cache_enable_ways();
-       if (ret) {
-               debug("%s: could not enable cache ways\n", __func__);
-               return ret;
-       }
+       enable_caches();
+
        return 0;
 }