pinctrl: renesas: Synchronize R8A77980 V3H PFC tables with Linux 6.5.3

Synchronize R-Car R8A77980 V3H PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c
index 19bd46c9e48cb6e4217d3b8913d07e09e808657e..523faa0ac8f66efa915d24584828f62ee4bbd1ee 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a77980.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77980.c
@@ -21,10 +21,10 @@
 #include "sh_pfc.h"
 
 #define CPU_ALL_GP(fn, sfx)    \
-       PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
+       PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),      \
        PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
-       PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
-       PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+       PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN),      \
+       PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
        PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
        PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
 
@@ -37,7 +37,9 @@
        PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),        \
        PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),      \
        PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),   \
-       PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
+       PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+       PIN_NOGP_CFG(VDDQ_AVB, "VDDQ_AVB", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33), \
+       PIN_NOGP_CFG(VDDQ_GE, "VDDQ_GE", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
 
 /*
  * F_() : just information
@@ -99,7 +101,7 @@
 #define GPSR1_0                F_(IRQ0,                IP2_27_24)
 
 /* GPSR2 */
-#define GPSR2_29       F_(FSO_TOE_N,           IP10_19_16)
+#define GPSR2_29       F_(FSO_TOE_N,           IP10_19_16)
 #define GPSR2_28       F_(FSO_CFE_1_N,         IP10_15_12)
 #define GPSR2_27       F_(FSO_CFE_0_N,         IP10_11_8)
 #define GPSR2_26       F_(SDA3,                IP10_7_4)
@@ -264,11 +266,11 @@
 #define IP8_11_8       FM(CANFD0_RX_A)                 FM(RXDA_EXTFXR)         FM(PWM1_B)              FM(DU_CDE)      F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP8_15_12      FM(CANFD1_TX)                   FM(FXR_TXDB)            FM(PWM2_B)              FM(TCLK1_B)     FM(TX1_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP8_19_16      FM(CANFD1_RX)                   FM(RXDB_EXTFXR)         FM(PWM3_B)              FM(TCLK2_B)     FM(RX1_B)       F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP8_23_20      FM(CANFD_CLK_A)                 FM(CLK_EXTFXR)          FM(PWM4_B)              FM(SPEEDIN_B)   FM(SCIF_CLK_B)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP8_23_20      FM(CANFD_CLK_A)                 FM(CLK_EXTFXR)          FM(PWM4_B)              FM(SPEEDIN_B)   FM(SCIF_CLK_B)  F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP8_27_24      FM(DIGRF_CLKIN)                 FM(DIGRF_CLKEN_IN)      F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP8_31_28      FM(DIGRF_CLKOUT)                FM(DIGRF_CLKEN_OUT)     F_(0, 0)                F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_3_0                FM(IRQ4)                        F_(0, 0)                F_(0, 0)                FM(VI0_DATA12)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_7_4        FM(IRQ5)                        F_(0, 0)                F_(0, 0)                FM(VI0_DATA13)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_7_4                FM(IRQ5)                        F_(0, 0)                F_(0, 0)                FM(VI0_DATA13)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_11_8       FM(MSIOF0_RXD)                  FM(DU_DR0)              F_(0, 0)                FM(VI0_DATA14)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_15_12      FM(MSIOF0_TXD)                  FM(DU_DR1)              F_(0, 0)                FM(VI0_DATA15)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_19_16      FM(MSIOF0_SCK)                  FM(DU_DG0)              F_(0, 0)                FM(VI0_DATA16)  F_(0, 0)        F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -2815,7 +2817,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                MOD_SEL0_1
                MOD_SEL0_0 ))
        },
-       { },
+       { /* sentinel */ }
 };
 
 enum ioctrl_regs {
@@ -2832,31 +2834,46 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
        [POCCTRL2] = { 0xe6060388, },
        [POCCTRL3] = { 0xe606038c, },
        [TDSELCTRL] = { 0xe60603c0, },
-       { /* sentinel */ },
+       { /* sentinel */ }
 };
 
 static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
 {
        int bit = pin & 0x1f;
 
-       *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
-       if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
+       switch (pin) {
+       case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
                return bit;
-       else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
+
+       case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
                return bit + 22;
 
-       *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
-       if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
+       case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
                return bit - 10;
-       if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
-           (pin >= RCAR_GP_PIN(3,  0) && pin <= RCAR_GP_PIN(3, 16)))
+
+       case RCAR_GP_PIN(2, 17) ... RCAR_GP_PIN(2, 24):
+       case RCAR_GP_PIN(3,  0) ... RCAR_GP_PIN(3, 16):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
                return bit + 7;
 
-       *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
-       if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
+       case RCAR_GP_PIN(2, 25) ... RCAR_GP_PIN(2, 29):
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
                return pin - 25;
 
-       return -EINVAL;
+       case PIN_VDDQ_AVB:
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
+               return 0;
+
+       case PIN_VDDQ_GE:
+               *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg;
+               return 1;
+
+       default:
+               return -EINVAL;
+       }
 }
 
 static const struct pinmux_bias_reg pinmux_bias_regs[] = {