Enable 8544 support

* Add support to the Makefile
* Add 8544 configuration support to the tsec driver
* Add 8544 SVR numbers to processor.h

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>

diff --git a/MAKEALL b/MAKEALL
index 0f0ec296f26b050c01266681958de8f482d0c92e..59aec2867f0134d3c7465f4e60d9e0a0edee458b 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -142,10 +142,10 @@ LIST_83xx="       \
 #########################################################################
 
 LIST_85xx="    \
-       MPC8540ADS      MPC8540EVAL     MPC8541CDS      MPC8548CDS      \
-       MPC8555CDS      MPC8560ADS      PM854           PM856           \
-       sbc8540         sbc8560         stxgp3          TQM8540         \
-       TQM8541         TQM8555         TQM8560                         \
+       MPC8540ADS      MPC8540EVAL     MPC8541CDS      MPC8544DS       \
+       MPC8548CDS      MPC8555CDS      MPC8560ADS      PM854           \
+       PM856           sbc8540         sbc8560         stxgp3          \
+       TQM8540         TQM8541         TQM8555         TQM8560         \
 "
 
 #########################################################################

diff --git a/Makefile b/Makefile
index 94cda54c731f19e08bb04c207ca7beb8d85e8020..d447a9610d4cbdcef93d939765c1f567ba069b85 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1730,6 +1730,9 @@ MPC8560ADS_config:        unconfig
 MPC8541CDS_config:     unconfig
        @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds
 
+MPC8544DS_config:      unconfig
+       @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
+
 MPC8548CDS_config:     unconfig
        @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds
 

diff --git a/drivers/tsec.c b/drivers/tsec.c
index 3f11eb03b41da825fee54a06daa9a5161b583be0..ed35f227c1b0f3840547d90e6fcedaea21361fd4 100644 (file)
--- a/drivers/tsec.c
+++ b/drivers/tsec.c
@@ -5,7 +5,7 @@
  * terms of the GNU Public License, Version 2, incorporated
  * herein by reference.
  *
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
  * (C) Copyright 2003, Motorola, Inc.
  * author Andy Fleming
  *
@@ -66,7 +66,11 @@ struct tsec_info_struct {
  */
 static struct tsec_info_struct tsec_info[] = {
 #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
+#if defined(CONFIG_MPC8544DS)
+        {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
+#else
        {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
+#endif
 #elif defined(CONFIG_MPC86XX_TSEC1)
        {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
 #else

diff --git a/drivers/tsec.h b/drivers/tsec.h
index 422bc6692292bc43b2f6271ed01d2c6fe4a6dbc9..7bf3dee2b6859ae67860c0b12a69ab1791ccfea3 100644 (file)
--- a/drivers/tsec.h
+++ b/drivers/tsec.h
@@ -7,7 +7,7 @@
  *  terms of the GNU Public License, Version 2, incorporated
  *  herein by reference.
  *
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor, Inc.
  * (C) Copyright 2003, Motorola, Inc.
  * maintained by Xianghua Xiao (x.xiao@motorola.com)
  * author Andy Fleming
@@ -65,6 +65,7 @@
 #define ECNTRL_INIT_SETTINGS   0x00001000
 #define ECNTRL_TBI_MODE         0x00000020
 #define ECNTRL_R100            0x00000008
+#define ECNTRL_SGMII_MODE      0x00000002
 
 #define miim_end -2
 #define miim_read -1

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 058596275f48d63711a263db92a438247be4ac0c..944cbe90c38a4fc7af98d6ff8700c57983363f0e 100644 (file)
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -232,6 +232,9 @@
 #define   HID0_BHTE    (1<<2)          /* Branch History Table Enable */
 #define   HID0_BTCD    (1<<1)          /* Branch target cache disable */
 #define SPRN_HID1      0x3F1   /* Hardware Implementation Register 1 */
+#define          HID1_RFXE     (1<<17)         /* Read Fault Exception Enable */
+#define          HID1_ASTME    (1<<13)         /* Address bus streaming mode */
+#define          HID1_ABE      (1<<12)         /* Address broadcast enable */
 #define SPRN_IABR      0x3F2   /* Instruction Address Breakpoint Register */
 #ifndef CONFIG_BOOKE
 #define SPRN_IAC1      0x3F4   /* Instruction Address Compare 1 */
@@ -415,10 +418,12 @@
 #define SPRN_IVOR15    0x19f   /* Interrupt Vector Offset Register 15 */
 
 /* e500 definitions */
-#define SPRN_L1CSR0     0x3f2   /* L1 Cache Control and Status Register 0 */
+#define SPRN_L1CSR0     0x3f2   /* L1 Data Cache Control and Status Register 0 */
+#define   L1CSR0_CPE            0x00010000     /* Data Cache Parity Enable */
 #define   L1CSR0_DCFI           0x00000002      /* Data Cache Flash Invalidate */
 #define   L1CSR0_DCE            0x00000001      /* Data Cache Enable */
-#define SPRN_L1CSR1     0x3f3   /* L1 Cache Control and Status Register 1 */
+#define SPRN_L1CSR1     0x3f3   /* L1 Instruction Cache Control and Status Register 1 */
+#define   L1CSR1_CPE            0x00010000     /* Instruction Cache Parity Enable */
 #define   L1CSR1_ICFI           0x00000002      /* Instruction Cache Flash Invalidate */
 #define   L1CSR1_ICE            0x00000001      /* Instruction Cache Enable */
 
@@ -840,6 +845,8 @@
 #define SVR_8560       0x8070
 #define SVR_8555       0x8079
 #define SVR_8541       0x807A
+#define SVR_8544       0x8034
+#define SVR_8544_E     0x803C
 #define SVR_8548       0x8031
 #define SVR_8548_E     0x8039
 #define SVR_8641       0x8090