rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)

Create a non-cacheable mapping for the 0x600000000 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
32bit mode, this region is mapped at 0xff800000 CPU virtual address.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index e6eb904e7f9f4a2bf5a3a6e863b83429400e6218..b3287ce8bcea9d6cf5af272ba08bc7dd44e559b1 100644 (file)
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -36,6 +36,7 @@ config BCM2711_32B
        select BCM2711
        select ARMV7_LPAE
        select CPU_V7A
+       select PHYS_64BIT
 
 config BCM2711_64B
        bool "Broadcom BCM2711 SoC 64-bit support"

diff --git a/arch/arm/mach-bcm283x/include/mach/base.h b/arch/arm/mach-bcm283x/include/mach/base.h
index c4ae39852f159158c1a78fcd088d7049e62765b7..4ccaf69693db4dd5dcf4a7b58bdb607d395dd0a9 100644 (file)
--- a/arch/arm/mach-bcm283x/include/mach/base.h
+++ b/arch/arm/mach-bcm283x/include/mach/base.h
@@ -8,4 +8,12 @@
 
 extern unsigned long rpi_bcm283x_base;
 
+#ifdef CONFIG_ARMV7_LPAE
+#ifdef CONFIG_TARGET_RPI_4_32B
+#include <addr_map.h>
+#define phys_to_virt addrmap_phys_to_virt
+#define virt_to_phys addrmap_virt_to_phys
+#endif
+#endif
+
 #endif

diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index f4d00d892dc7aca725e9131b29a2d2f71bae68ae..fc83392db2dd36ec8fdfbd32c9f890e54e81067f 100644 (file)
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -134,6 +134,27 @@ int mach_cpu_init(void)
 }
 
 #ifdef CONFIG_ARMV7_LPAE
+#ifdef CONFIG_TARGET_RPI_4_32B
+#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT       0xff800000UL
+#include <addr_map.h>
+#include <asm/system.h>
+
+void init_addr_map(void)
+{
+       mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
+                                            BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+                                            BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
+                                            DCACHE_OFF);
+
+       /* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
+       addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
+       /* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
+       addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
+                         BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
+                         BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
+}
+#endif
+
 void enable_caches(void)
 {
        dcache_enable();