Divisor field is called PTV not PVT.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
/* Start the counter ticking up */
*((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/
- val = (CONFIG_SYS_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/
+ val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/
*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */
reset_timer_masked(); /* init the timestamp and lastinc value */
/* Start the decrementer ticking down from 0xffffffff */
*((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
- val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT);
+ val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT);
*((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
/* init the timestamp and lastdec value */
/* Start the decrementer ticking down from 0xffffffff */
*((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
- val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT);
+ val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PTV << MPUTIM_PTV_BIT);
*((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
/* init the timestamp and lastdec value */
/* start the counter ticking up, reload value on overflow */
writel(TIMER_LOAD_VAL, &timer_base->tldr);
/* enable timer */
- writel((CONFIG_SYS_PVT << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
+ writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
&timer_base->tclr);
reset_timer_masked(); /* init the timestamp and lastinc value */
/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
* This time is further subdivided by a local divisor.
*/
-#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
-#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */
+#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
+#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
* or by 32KHz clk, or from external sig. This rate is divided by a local
* divisor.
*/
-#define V_PVT 7 /* use with 12MHz/128 */
-
#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
-#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
+#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
* This time is further subdivided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE
-#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_PTV 7 /* 2^(pvt+1), divide by 256 */
+#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
#define OMAP5910_DPLL_DIV 1
#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \
/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
* This time is further subdivided by a local divisor.
*/
-#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
-#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */
+#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
+#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
* DPLL1. This time is further subdivided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
-#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
+#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
* DPLL1. This time is further subdivided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
-#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
+#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
#ifdef CONFIG_APTIX
-#define V_PVT 3
+#define V_PTV 3
#else
-#define V_PVT 7 /* use with 12MHz/128 */
+#define V_PTV 7 /* use with 12MHz/128 */
#endif
-#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
-#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
+#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */
+#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
-#define V_PVT 7
-
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
-#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
+#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
-#define V_PVT 7
-
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
-#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
-#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
+#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
-#define V_PVT 7
-
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
-#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
+#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
-#define V_PVT 7
-
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
-#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
+#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
-#define V_PVT 7
-
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */
-#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
+#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
* DPLL1. This time is further subdivided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
-#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
+#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
* the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
* local divisor.
*/
-
-#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
-#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
+#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
+#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
* This time is further subdivided by a local divisor.
*/
-#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE
-#define CONFIG_SYS_PVT 7 /* 2^(pvt+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
+#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE
+#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
+#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
#define OMAP5910_DPLL_DIV 1
#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \
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