ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value

The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index e601ba1886fb82a9b552b099dc1b14a09dfedd3b..c01a98f71958e67df5674f4330d463ffa1512a32 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -252,6 +252,8 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
 {
        struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
+       writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+       writel(regs->sdram_config_init, &emif->emif_sdram_config);
        /*
         * Set SDRAM_CONFIG and PHY control registers to locked frequency
         * and RL =7. As the default values of the Mode Registers are not
@@ -265,7 +267,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
        writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
        writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 
-       writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
        writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 
        /*
@@ -274,6 +275,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
         */
        if (is_dra7xx()) {
                do_ext_phy_settings(base, regs);
+               writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
                writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
                writel(regs->sdram_config_init, &emif->emif_sdram_config);
        } else {

diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index e5456ff7cb616eeb6a8e210a8ef3904e286cffb0..61e9aefe0916e15fcb346caee8020fb5c3f22ae2 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -141,7 +141,8 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .sdram_config_init              = 0x61851ab2,
        .sdram_config                   = 0x61851ab2,
        .sdram_config2                  = 0x08000000,
-       .ref_ctrl                       = 0x00001035,
+       .ref_ctrl                       = 0x000040F1,
+       .ref_ctrl_final                 = 0x00001035,
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
        .sdram_tim3                     = 0x027F88A8,
@@ -165,7 +166,8 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .sdram_config_init              = 0x61851B32,
        .sdram_config                   = 0x61851B32,
        .sdram_config2                  = 0x08000000,
-       .ref_ctrl                       = 0x00001035,
+       .ref_ctrl                       = 0x000040F1,
+       .ref_ctrl_final                 = 0x00001035,
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
        .sdram_tim3                     = 0x027F88A8,
@@ -189,7 +191,8 @@ const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
        .sdram_config_init              = 0x61862B32,
        .sdram_config                   = 0x61862B32,
        .sdram_config2                  = 0x08000000,
-       .ref_ctrl                       = 0x0000144A,
+       .ref_ctrl                       = 0x0000493E,
+       .ref_ctrl_final                 = 0x0000144A,
        .sdram_tim1                     = 0xD113781C,
        .sdram_tim2                     = 0x308F7FE3,
        .sdram_tim3                     = 0x009F86A8,

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 342f045f41419471adea238aed0fcb309e7185d2..7a545ea01a7c3f661867696f9c88c80fd3386dae 100644 (file)
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -1149,6 +1149,7 @@ struct emif_regs {
        u32 sdram_config;
        u32 sdram_config2;
        u32 ref_ctrl;
+       u32 ref_ctrl_final;
        u32 sdram_tim1;
        u32 sdram_tim2;
        u32 sdram_tim3;

diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c
index db96e347e7ab10b7ea7dc1f5e1205050d5008f95..3a7e04d542dde214d04b808bf47cf15b01019b89 100644 (file)
--- a/board/ti/beagle_x15/board.c
+++ b/board/ti/beagle_x15/board.c
@@ -47,7 +47,8 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
        .sdram_config_init      = 0x61851b32,
        .sdram_config           = 0x61851b32,
        .sdram_config2          = 0x00000000,
-       .ref_ctrl               = 0x00001035,
+       .ref_ctrl               = 0x000040F1,
+       .ref_ctrl_final         = 0x00001035,
        .sdram_tim1             = 0xceef266b,
        .sdram_tim2             = 0x328f7fda,
        .sdram_tim3             = 0x027f88a8,
@@ -103,7 +104,8 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
        .sdram_config_init      = 0x61851b32,
        .sdram_config           = 0x61851b32,
        .sdram_config2          = 0x00000000,
-       .ref_ctrl               = 0x00001035,
+       .ref_ctrl               = 0x000040F1,
+       .ref_ctrl_final         = 0x00001035,
        .sdram_tim1             = 0xceef266b,
        .sdram_tim2             = 0x328f7fda,
        .sdram_tim3             = 0x027f88a8,