OMAP5: Change voltages for omap5432

Change voltages for OMAP5432

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c
index 1a59f265f7b00ca6bc020f77428eee4bb454b640..65dc5c759532434d18a6025a78ca308cada0a5b7 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/clocks.c
+++ b/arch/arm/cpu/armv7/omap5/clocks.c
@@ -260,20 +260,31 @@ const struct dpll_params *get_abe_dpll_params(void)
  */
 void scale_vcores(void)
 {
-       u32 volt;
+       u32 volt_core, volt_mpu, volt_mm;
 
        omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
 
        /* Palmas settings */
-       volt = VDD_CORE;
-       do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt);
-
-       volt = VDD_MPU;
-       do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt);
-
-       volt = VDD_MM;
-       do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt);
-
+       if (omap_revision() != OMAP5432_ES1_0) {
+               volt_core = VDD_CORE;
+               volt_mpu = VDD_MPU;
+               volt_mm = VDD_MM;
+       } else {
+               volt_core = VDD_CORE_5432;
+               volt_mpu = VDD_MPU_5432;
+               volt_mm = VDD_MM_5432;
+       }
+
+       do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core);
+       do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
+       do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
+
+       if (omap_revision() == OMAP5432_ES1_0) {
+               /* Configure LDO SRAM "magic" bits */
+               writel(2, &prcm->prm_sldo_core_setup);
+               writel(2, &prcm->prm_sldo_mpu_setup);
+               writel(2, &prcm->prm_sldo_mm_setup);
+       }
 }
 
 u32 get_offset_code(u32 volt_offset)

diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index 409e0e3f8c11336e7f1ff889c6f74596e2df2faf..5f1a7aa770dcf6e0c345be2dc86d9df97d49c61a 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -480,6 +480,13 @@ struct omap5_prcm_regs {
        u32 pad217[4];
        u32 prm_vc_cfg_i2c_mode;                /* 4ae07bb4 */
        u32 prm_vc_cfg_i2c_clk;                 /* 4ae07bb8 */
+       u32 pad218[2];
+       u32 prm_sldo_core_setup;                /* 4ae07bc4 */
+       u32 prm_sldo_core_ctrl;                 /* 4ae07bc8 */
+       u32 prm_sldo_mpu_setup;                 /* 4ae07bcc */
+       u32 prm_sldo_mpu_ctrl;                  /* 4ae07bd0 */
+       u32 prm_sldo_mm_setup;                  /* 4ae07bd4 */
+       u32 prm_sldo_mm_ctrl;                   /* 4ae07bd8 */
 };
 
 /* DPLL register offsets */
@@ -646,6 +653,9 @@ struct omap5_prcm_regs {
 #define VDD_MPU                1000
 #define VDD_MM         1000
 #define VDD_CORE       1040
+#define VDD_MPU_5432   1150
+#define VDD_MM_5432    1150
+#define VDD_CORE_5432  1150
 
 /* Standard offset is 0.5v expressed in uv */
 #define PALMAS_SMPS_BASE_VOLT_UV 500000