arm: dts: Stratix10: change pad skew values for EMAC0 PHY driver

The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA
drive strength has caused CE test to fail. This requires changes on the
pad skew for EMAC0 PHY driver. Based on several measurements done, Tx
clock does not require the extra 0.96ns delay which was needed in
Arria10.

Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>

diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts
index ce07659602b013e1c41903756267a3c9421fe0dc..58baa710d4092d876c1511f72ae39149e2c2f7e8 100755 (executable)
--- a/arch/arm/dts/socfpga_stratix10_socdk.dts
+++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
@@ -73,7 +73,7 @@
                        rxd2-skew-ps = <420>; /* 0ps */
                        rxd3-skew-ps = <420>; /* 0ps */
                        txen-skew-ps = <0>; /* -420ps */
-                       txc-skew-ps = <1860>; /* 960ps */
+                       txc-skew-ps = <900>; /* 0ps */
                        rxdv-skew-ps = <420>; /* 0ps */
                        rxc-skew-ps = <1680>; /* 780ps */
                };