board: freescale: ls1012a: Enable secure DDR on LS1012A platforms

PPA binary needs to be relocated on secure DDR, hence marking out
a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag
is set

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 8c426af47e78b906ca9e578f36954f9c81b9c957..83f55016124239f8e7fdacccfe7af7534035876d 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -192,6 +192,9 @@
 #define GICD_BASE              0x01401000
 #define GICC_BASE              0x01402000
 
+#define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
+
 #elif defined(CONFIG_ARCH_LS1046A)
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_NUM_FMAN                    1

diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index b03bdb82c67c903856277a9ae58c80c8dd6448f2..c2432c3e734cbb4769a638e59e8f1c68e6083887 100644 (file)
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -85,3 +85,32 @@ int ft_board_setup(void *blob, bd_t *bd)
 
        return 0;
 }
+
+void dram_init_banksize(void)
+{
+       /*
+        * gd->arch.secure_ram tracks the location of secure memory.
+        * It was set as if the memory starts from 0.
+        * The address needs to add the offset of its bank.
+        */
+       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+       if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+               gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+               gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+               gd->bd->bi_dram[1].size = gd->ram_size -
+                       CONFIG_SYS_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+               gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+                       gd->arch.secure_ram -
+                       CONFIG_SYS_DDR_BLOCK1_SIZE;
+               gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+       } else {
+               gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+               gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+                       gd->arch.secure_ram;
+               gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+       }
+}

diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 88fb4ce99b91acd7d65e729cc37dffd32edf788f..bdd95296417cd0aa95760cad2485c1c6abd1a112 100644 (file)
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -159,3 +159,32 @@ int ft_board_setup(void *blob, bd_t *bd)
        return 0;
 }
 #endif
+
+void dram_init_banksize(void)
+{
+       /*
+        * gd->arch.secure_ram tracks the location of secure memory.
+        * It was set as if the memory starts from 0.
+        * The address needs to add the offset of its bank.
+        */
+       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+       if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+               gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+               gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+               gd->bd->bi_dram[1].size = gd->ram_size -
+                       CONFIG_SYS_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+               gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+                       gd->arch.secure_ram -
+                       CONFIG_SYS_DDR_BLOCK1_SIZE;
+               gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+       } else {
+               gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+               gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+                       gd->arch.secure_ram;
+               gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+       }
+}

diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 65fa94c61812bee5336b8eff541a6f2457163b37..2dece02f8359fec1dfebafabb3b7fbc864db0652 100644 (file)
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -159,3 +159,32 @@ int ft_board_setup(void *blob, bd_t *bd)
 
        return 0;
 }
+
+void dram_init_banksize(void)
+{
+       /*
+        * gd->secure_ram tracks the location of secure memory.
+        * It was set as if the memory starts from 0.
+        * The address needs to add the offset of its bank.
+        */
+       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+       if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+               gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+               gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+               gd->bd->bi_dram[1].size = gd->ram_size -
+                       CONFIG_SYS_DDR_BLOCK1_SIZE;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+               gd->arch.secure_ram = gd->bd->bi_dram[1].start +
+                       gd->arch.secure_ram -
+                       CONFIG_SYS_DDR_BLOCK1_SIZE;
+               gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+       } else {
+               gd->bd->bi_dram[0].size = gd->ram_size;
+#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
+               gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+                       gd->arch.secure_ram;
+               gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
+#endif
+       }
+}

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 81f8d6263e58f843d743075092a165f5153d6632..0965afafb14ec72a7c2df9fc2946d0aa23424a49 100644 (file)
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -29,6 +29,7 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY      0
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE     0x880000000ULL
 
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY              CONFIG_SYS_CLK_FREQ/4   /* 25MHz */