reg-shift = <3>;
interrupts = <0x08040 4>;
};
+
+ i2c0: i2c@1180000001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "cavium,octeon-7890-twsi";
+ reg = <0x11800 0x00001000 0x0 0x200>;
+ /* INT_ST, INT_TS, INT_CORE */
+ interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@1180000001200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "cavium,octeon-7890-twsi";
+ reg = <0x11800 0x00001200 0x0 0x200>;
+ /* INT_ST, INT_TS, INT_CORE */
+ interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>;
+ clock-frequency = <100000>;
+ };
};
};
&uart0 {
clock-frequency = <1200000000>;
};
+
+&i2c0 {
+ u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
+ clock-frequency = <100000>;
+};
+
+&i2c1 {
+ u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
+ clock-frequency = <100000>;
+};