arm64: dts: st: add bsec support to stm32mp25

Add BSEC support to STM32MP25 SoC family with SoC information:
- RPN = Device part number (BSEC_OTP_DATA9)
- PKG = package data register (Bits 2:0 of BSEC_OTP_DATA122)

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

diff --git a/arch/arm/dts/stm32mp25-u-boot.dtsi b/arch/arm/dts/stm32mp25-u-boot.dtsi
index f4f26add2a415b6cef7b7915b23dbd2f26ea62a1..0c8e95b34163206ac3dcd625b4867bdb73be2086 100644 (file)
--- a/arch/arm/dts/stm32mp25-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp25-u-boot.dtsi
@@ -37,6 +37,10 @@
        };
 };
 
+&bsec {
+       bootph-all;
+};
+
 &gpioa {
        bootph-all;
 };

diff --git a/arch/arm/dts/stm32mp251.dtsi b/arch/arm/dts/stm32mp251.dtsi
index cf2f28dc1582d121006c51b045d6e9461c5d6c0f..44eb664fb510273706229fde435e588e7f0def0b 100644 (file)
--- a/arch/arm/dts/stm32mp251.dtsi
+++ b/arch/arm/dts/stm32mp251.dtsi
@@ -127,6 +127,22 @@
                        };
                };
 
+               bsec: efuse@44000000 {
+                       compatible = "st,stm32mp25-bsec";
+                       reg = <0x44000000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       part_number_otp@24 {
+                               reg = <0x24 0x4>;
+                       };
+
+                       package_otp@1e8 {
+                               reg = <0x1e8 0x1>;
+                               bits = <0 3>;
+                       };
+               };
+
                syscfg: syscon@44230000 {
                        compatible = "st,stm32mp25-syscfg", "syscon";
                        reg = <0x44230000 0x10000>;