rockchip: sdhci: rk3568: fix clock setting logic

mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post
uses it if its != 0, regardless of mmc->clock value, and it breaks
eMMC controller.

Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for
breaking eMMC, since first initialization sets mmc->mmc_tran speed
to non-zero value (26MHz in my case), and on subsequent re-init when
mmc layer asks for 400KHz it sets 26MHz instead.

Fix it by using MAX(mmc->tran_speed, mmc->clock)

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index e1409dd2c749ce2144fe4e2a6c42581769390ea0..fef23f593e837863b474750196c344015d36d71a 100644 (file)
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -401,11 +401,11 @@ static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host)
 static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
 {
        struct mmc *mmc = host->mmc;
-       uint clock = mmc->tran_speed;
+       uint clock = mmc->clock;
        u32 reg, vendor_reg;
 
-       if (!clock)
-               clock = mmc->clock;
+       if (mmc->tran_speed && mmc->clock > mmc->tran_speed)
+               clock = mmc->tran_speed;
 
        rk3568_sdhci_emmc_set_clock(host, clock);