COBJS-y += afeb9260.o
COBJS-y += partition.o
-COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
/* Configure RDY/BSY */
- at91_set_gpio_input(AT91_PIN_PC13, 1);
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(AT91_PIN_PC14, 1);
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#ifdef CONFIG_MACB
COBJS-y += at91cap9adk.o
COBJS-y += led.o
COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
-COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
/* RDY/BSY is not connected */
/* Enable NandFlash */
- at91_set_gpio_output(AT91_PIN_PD15, 1);
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91cap9.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91_pio.h>
-
-#include <nand.h>
-
-/*
- * hardware specific access to control-lines
- */
-#define MASK_ALE (1 << 21) /* our ALE is AD21 */
-#define MASK_CLE (1 << 22) /* our CLE is AD22 */
-
-static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd,
- int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
-
- if (ctrl & NAND_CLE)
- IO_ADDR_W |= MASK_CLE;
- if (ctrl & NAND_ALE)
- IO_ADDR_W |= MASK_ALE;
-
- at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
- this->IO_ADDR_W = (void *) IO_ADDR_W;
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- nand->ecc.mode = NAND_ECC_SOFT;
-#ifdef CONFIG_SYS_NAND_DBW_16
- nand->options = NAND_BUSWIDTH_16;
-#endif
- nand->cmd_ctrl = at91cap9adk_nand_hwcontrol;
- nand->chip_delay = 20;
-
- return 0;
-}
COBJS-y += at91sam9260ek.o
COBJS-y += led.o
COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
-COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
/* Configure RDY/BSY */
- at91_set_gpio_input(AT91_PIN_PC13, 1);
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(AT91_PIN_PC14, 1);
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91sam9260.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91_pio.h>
-
-#include <nand.h>
-
-/*
- * hardware specific access to control-lines
- */
-#define MASK_ALE (1 << 21) /* our ALE is AD21 */
-#define MASK_CLE (1 << 22) /* our CLE is AD22 */
-
-static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd,
- int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
-
- if (ctrl & NAND_CLE)
- IO_ADDR_W |= MASK_CLE;
- if (ctrl & NAND_ALE)
- IO_ADDR_W |= MASK_ALE;
-
- at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
- this->IO_ADDR_W = (void *) IO_ADDR_W;
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
-{
- return at91_get_gpio_value(AT91_PIN_PC13);
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- nand->ecc.mode = NAND_ECC_SOFT;
-#ifdef CONFIG_SYS_NAND_DBW_16
- nand->options = NAND_BUSWIDTH_16;
-#endif
- nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol;
- nand->dev_ready = at91sam9260ek_nand_ready;
- nand->chip_delay = 20;
-
- return 0;
-}
COBJS-y += at91sam9261ek.o
COBJS-y += led.o
COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
-COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
/* Configure RDY/BSY */
- at91_set_gpio_input(AT91_PIN_PC15, 1);
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(AT91_PIN_PC14, 1);
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91sam9261.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91_pio.h>
-
-#include <nand.h>
-
-/*
- * hardware specific access to control-lines
- */
-#define MASK_ALE (1 << 22) /* our ALE is AD22 */
-#define MASK_CLE (1 << 21) /* our CLE is AD21 */
-
-static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd,
- int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
-
- if (ctrl & NAND_CLE)
- IO_ADDR_W |= MASK_CLE;
- if (ctrl & NAND_ALE)
- IO_ADDR_W |= MASK_ALE;
-
- at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
- this->IO_ADDR_W = (void *) IO_ADDR_W;
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
-{
- return at91_get_gpio_value(AT91_PIN_PC15);
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- nand->ecc.mode = NAND_ECC_SOFT;
-#ifdef CONFIG_SYS_NAND_DBW_16
- nand->options = NAND_BUSWIDTH_16;
-#endif
- nand->cmd_ctrl = at91sam9261ek_nand_hwcontrol;
- nand->dev_ready = at91sam9261ek_nand_ready;
- nand->chip_delay = 20;
-
- return 0;
-}
COBJS-y += at91sam9263ek.o
COBJS-y += led.o
COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
-COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
1 << AT91SAM9263_ID_PIOCDE);
/* Configure RDY/BSY */
- at91_set_gpio_input(AT91_PIN_PA22, 1);
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(AT91_PIN_PD15, 1);
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91sam9263.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91_pio.h>
-
-#include <nand.h>
-
-/*
- * hardware specific access to control-lines
- */
-#define MASK_ALE (1 << 21) /* our ALE is AD21 */
-#define MASK_CLE (1 << 22) /* our CLE is AD22 */
-
-static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd,
- int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
-
- if (ctrl & NAND_CLE)
- IO_ADDR_W |= MASK_CLE;
- if (ctrl & NAND_ALE)
- IO_ADDR_W |= MASK_ALE;
-
- at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
- this->IO_ADDR_W = (void *) IO_ADDR_W;
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
-{
- return at91_get_gpio_value(AT91_PIN_PA22);
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- nand->ecc.mode = NAND_ECC_SOFT;
-#ifdef CONFIG_SYS_NAND_DBW_16
- nand->options = NAND_BUSWIDTH_16;
-#endif
- nand->cmd_ctrl = at91sam9263ek_nand_hwcontrol;
- nand->dev_ready = at91sam9263ek_nand_ready;
- nand->chip_delay = 20;
-
- return 0;
-}
COBJS-y += at91sam9rlek.o
COBJS-y += led.o
COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
-COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_PIOD);
/* Configure RDY/BSY */
- at91_set_gpio_input(AT91_PIN_PD17, 1);
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(AT91_PIN_PB6, 1);
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
+++ /dev/null
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/at91sam9rl.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/at91_pio.h>
-
-#include <nand.h>
-
-/*
- * hardware specific access to control-lines
- */
-#define MASK_ALE (1 << 21) /* our ALE is AD21 */
-#define MASK_CLE (1 << 22) /* our CLE is AD22 */
-
-static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd,
- int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
-
- if (ctrl & NAND_CLE)
- IO_ADDR_W |= MASK_CLE;
- if (ctrl & NAND_ALE)
- IO_ADDR_W |= MASK_ALE;
-
- at91_set_gpio_value(AT91_PIN_PB6, !(ctrl & NAND_NCE));
- this->IO_ADDR_W = (void *) IO_ADDR_W;
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
-{
- return at91_get_gpio_value(AT91_PIN_PD17);
-}
-
-int board_nand_init(struct nand_chip *nand)
-{
- nand->ecc.mode = NAND_ECC_SOFT;
-#ifdef CONFIG_SYS_NAND_DBW_16
- nand->options = NAND_BUSWIDTH_16;
-#endif
- nand->cmd_ctrl = at91sam9rlek_nand_hwcontrol;
- nand->dev_ready = at91sam9rlek_nand_ready;
- nand->chip_delay = 20;
-
- return 0;
-}
COBJS-y += nand_util.o
endif
+COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o
COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
*/
#include <common.h>
-#include <asm/arch/at91sam9260.h>
+#include <asm/arch/hardware.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pio.h>
#include <nand.h>
-/*
- * hardware specific access to control-lines
- */
-#define MASK_ALE (1 << 21) /* our ALE is AD21 */
-#define MASK_CLE (1 << 22) /* our CLE is AD22 */
-
-static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd,
+static void at91_nand_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+ IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
+ | CONFIG_SYS_NAND_MASK_CLE);
if (ctrl & NAND_CLE)
- IO_ADDR_W |= MASK_CLE;
+ IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
if (ctrl & NAND_ALE)
- IO_ADDR_W |= MASK_ALE;
+ IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
- at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
+ at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
+ !(ctrl & NAND_NCE));
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
writeb(cmd, this->IO_ADDR_W);
}
-static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
+#ifdef CONFIG_SYS_NAND_READY_PIN
+static int at91_nand_ready(struct mtd_info *mtd)
{
- return at91_get_gpio_value(AT91_PIN_PC13);
+ return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
}
+#endif
int board_nand_init(struct nand_chip *nand)
{
#ifdef CONFIG_SYS_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
- nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol;
- nand->dev_ready = at91sam9260ek_nand_ready;
+ nand->cmd_ctrl = at91_nand_hwcontrol;
+#ifdef CONFIG_SYS_NAND_READY_PIN
+ nand->dev_ready = at91_nand_ready;
+#endif
nand->chip_delay = 20;
return 0;
#define DATAFLASH_TCHS (0x1 << 24)
/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+#endif
/* NOR flash - no real flash on this board */
#define CONFIG_SYS_NO_FLASH 1
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_MAX_FLASH_BANKS 1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
+#endif
/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
#define DATAFLASH_TCHS (0x1 << 24)
/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
+#endif
/* NOR flash - no real flash on this board */
#define CONFIG_SYS_NO_FLASH 1
#define DATAFLASH_TCHS (0x1 << 24)
/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD22 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
+/* our CLE is AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15
+#endif
/* NOR flash - no real flash on this board */
#define CONFIG_SYS_NO_FLASH 1
#endif
/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
+#endif
/* Ethernet */
#define CONFIG_MACB 1
#define CONFIG_SYS_NO_FLASH 1
/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8 1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
+#endif
/* Ethernet - not present */
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