fpga: zynqmppl: fix fpga loads command for unencrypted use case

When using the fpga loads command, the driver is passing the AES encryption
key address is all cases.  However, for the authenticated, but not encrypted
use case, there is no AES encryption key, and this value is 0.

When AES encryption is not used on the fpga bitstream, the pmufw assumes that
the AES key address is a bitstream size value like what is used by the
unsecure fpga load command.

To fix the problem, this patch checks to see if the AES key address is zero.
If the AES key address is zero, it means that AES is not being used on the
bitstream and the bitstream size should be passed instead.  Thus, matching
the fpga load functionality.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230214131959.40298-1-neal.frager@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index d1491da02c316ca54e27560fbd8a956f80fd5824..7b5128fe27a1b2c4f1f1e6ddf6ec7e8e3a0ce568 100644 (file)
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -332,10 +332,16 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
        buf_lo = lower_32_bits((ulong)buf);
        buf_hi = upper_32_bits((ulong)buf);
 
-       ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
+       if ((u32)(uintptr_t)fpga_sec_info->userkey_addr)
+               ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
                                buf_hi,
-                        (u32)(uintptr_t)fpga_sec_info->userkey_addr,
-                        flag, ret_payload);
+                               (u32)(uintptr_t)fpga_sec_info->userkey_addr,
+                               flag, ret_payload);
+       else
+               ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
+                                       buf_hi, (u32)bsize,
+                                       flag, ret_payload);
+
        if (ret)
                puts("PL FPGA LOAD fail\n");
        else