]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
ddr: fsl: Impl. Erratum A008109
authorJoakim Tjernlund <joakim.tjernlund@infinera.com>
Wed, 20 Nov 2019 16:07:34 +0000 (17:07 +0100)
committerPriyanka Jain <priyanka.jain@nxp.com>
Thu, 4 Jun 2020 13:23:20 +0000 (18:53 +0530)
Impl. erratum as descibed in errata doc.
Enable A008109 for T1040 and T1024

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
arch/powerpc/cpu/mpc85xx/Kconfig
drivers/ddr/fsl/Kconfig
drivers/ddr/fsl/ctrl_regs.c

index 6fc6ea8fef709f89544a510b37e675c807521bf6..5bd69d51cbe5b8652d5f44353175e9d9c1d4058c 100644 (file)
@@ -1038,6 +1038,7 @@ config ARCH_T1040
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008044
        select SYS_FSL_ERRATUM_A008378
+       select SYS_FSL_ERRATUM_A008109
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_ESDHC111
@@ -1061,6 +1062,7 @@ config ARCH_T1042
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008044
        select SYS_FSL_ERRATUM_A008378
+       select SYS_FSL_ERRATUM_A008109
        select SYS_FSL_ERRATUM_A009663
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_ESDHC111
index 1b73df82debc1dc47658dce9616537b68c5b8dc8..f75d97b15c4daf5fd9899a920c3c806b1fcb21f7 100644 (file)
@@ -151,6 +151,9 @@ endmenu
 config SYS_FSL_ERRATUM_A008378
        bool
 
+config SYS_FSL_ERRATUM_A008109
+       bool
+
 config SYS_FSL_ERRATUM_A008511
        bool
 
index 2d3fb1953b85ab07f35f80e9c26b66219163209e..0e98ba4b4aee5344b73e090cf544283ec301e997 100644 (file)
@@ -2628,6 +2628,12 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
        }
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008109
+       ddr->ddr_sdram_cfg_2 = ddr_in32(&ddr->ddr_sdram_cfg_2) | 0x800; /* DDR_SLOW */
+       ddr->debug[18] = ddr_in32(&ddrc->debug[18]) | 0x2;
+       ddr->debug[28] = 0x30000000;
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
        ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
        ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);