clk: renesas: Synchronize R8A779A0 V3U clock tables with Linux 6.1.7

Synchronize R-Car R8A779A0 V3U clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .

Rename CLK_TYPE_R8A779A0_ to CLK_TYPE_GEN4_ to match the new
clock tables. Add CLK_TYPE_GEN4_SD, CLK_TYPE_GEN4_RPC and
CLK_TYPE_GEN4_RPCD2 macros and handling into Gen3 CPG core.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 84cf072cae6c671a3895823679f9a9f02b05d95f..94715bb00ce4f9f216f917a2c1af18923248d257 100644 (file)
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -253,23 +253,23 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
                                                CPG_PLL4CR, 0, 0, "PLL4");
 
-       case CLK_TYPE_R8A779A0_MAIN:
+       case CLK_TYPE_GEN4_MAIN:
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
                                                0, 1, pll_config->extal_div,
                                                "V3U_MAIN");
 
-       case CLK_TYPE_R8A779A0_PLL1:
+       case CLK_TYPE_GEN4_PLL1:
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
                                                0, pll_config->pll1_mult,
                                                pll_config->pll1_div,
                                                "V3U_PLL1");
 
-       case CLK_TYPE_R8A779A0_PLL2X_3X:
+       case CLK_TYPE_GEN4_PLL2X_3X:
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
                                                core->offset, 0, 0,
                                                "V3U_PLL2X_3X");
 
-       case CLK_TYPE_R8A779A0_PLL5:
+       case CLK_TYPE_GEN4_PLL5:
                return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
                                                0, pll_config->pll5_mult,
                                                pll_config->pll5_div,
@@ -290,11 +290,13 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
                return rate;
 
        case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */
+               fallthrough;
+       case CLK_TYPE_GEN4_SDH: /* Fixed factor 1:1 */
                return gen3_clk_get_rate64(&parent);
 
        case CLK_TYPE_GEN3_SD:          /* FIXME */
                fallthrough;
-       case CLK_TYPE_R8A779A0_SD:
+       case CLK_TYPE_GEN4_SD:
                value = readl(priv->base + core->offset);
                value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
 
@@ -315,6 +317,8 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
 
        case CLK_TYPE_GEN3_RPC:
        case CLK_TYPE_GEN3_RPCD2:
+       case CLK_TYPE_GEN4_RPC:
+       case CLK_TYPE_GEN4_RPCD2:
                rate = gen3_clk_get_rate64(&parent);
 
                value = readl(priv->base + core->offset);

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index bda699523625cda9f2027cefae988c06c5cf553c..0c28477377e67350be6da5cc81499d5c07ae46d6 100644 (file)
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -53,29 +53,18 @@ enum clk_ids {
 };
 
 #define DEF_PLL(_name, _id, _offset)   \
-       DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
+       DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
                 .offset = _offset)
 
-#define DEF_SD(_name, _id, _parent, _offset)   \
-       DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset)
-
-#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
-       DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL,   \
-                (_parent0) << 16 | (_parent1),         \
-                .div = (_div0) << 16 | (_div1), .offset = _md)
-
-#define DEF_OSC(_name, _id, _parent, _div)             \
-       DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div)
-
 static const struct cpg_core_clk r8a779a0_core_clks[] = {
        /* External Clock Inputs */
        DEF_INPUT("extal",  CLK_EXTAL),
        DEF_INPUT("extalr", CLK_EXTALR),
 
        /* Internal Core Clocks */
-       DEF_BASE(".main", CLK_MAIN,     CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
-       DEF_BASE(".pll1", CLK_PLL1,     CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
-       DEF_BASE(".pll5", CLK_PLL5,     CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
+       DEF_BASE(".main", CLK_MAIN,     CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
+       DEF_BASE(".pll1", CLK_PLL1,     CLK_TYPE_GEN4_PLL1, CLK_MAIN),
+       DEF_BASE(".pll5", CLK_PLL5,     CLK_TYPE_GEN4_PLL5, CLK_MAIN),
        DEF_PLL(".pll20", CLK_PLL20,    0x0834),
        DEF_PLL(".pll21", CLK_PLL21,    0x0838),
        DEF_PLL(".pll30", CLK_PLL30,    0x083c),
@@ -91,9 +80,14 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = {
        DEF_FIXED(".s1",                CLK_S1,         CLK_PLL1_DIV2,  2, 1),
        DEF_FIXED(".s3",                CLK_S3,         CLK_PLL1_DIV2,  4, 1),
        DEF_FIXED(".sdsrc",             CLK_SDSRC,      CLK_PLL5_DIV4,  1, 1),
+
        DEF_RATE(".oco",                CLK_OCO,        32768),
 
+       DEF_BASE(".rpcsrc",             CLK_RPCSRC,     CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
+
        /* Core Clock Outputs */
+       DEF_GEN4_Z("z0",        R8A779A0_CLK_Z0,        CLK_TYPE_GEN4_Z,        CLK_PLL20,      2, 0),
+       DEF_GEN4_Z("z1",        R8A779A0_CLK_Z1,        CLK_TYPE_GEN4_Z,        CLK_PLL21,      2, 8),
        DEF_FIXED("zx",         R8A779A0_CLK_ZX,        CLK_PLL20_DIV2, 2, 1),
        DEF_FIXED("s1d1",       R8A779A0_CLK_S1D1,      CLK_S1,         1, 1),
        DEF_FIXED("s1d2",       R8A779A0_CLK_S1D2,      CLK_S1,         2, 1),
@@ -107,7 +101,6 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = {
        DEF_FIXED("zt",         R8A779A0_CLK_ZT,        CLK_PLL1_DIV2,  2, 1),
        DEF_FIXED("ztr",        R8A779A0_CLK_ZTR,       CLK_PLL1_DIV2,  2, 1),
        DEF_FIXED("zr",         R8A779A0_CLK_ZR,        CLK_PLL1_DIV2,  1, 1),
-       DEF_FIXED("dsi",        R8A779A0_CLK_DSI,       CLK_PLL5_DIV4,  1, 1),
        DEF_FIXED("cnndsp",     R8A779A0_CLK_CNNDSP,    CLK_PLL5_DIV4,  1, 1),
        DEF_FIXED("vip",        R8A779A0_CLK_VIP,       CLK_PLL5,       5, 1),
        DEF_FIXED("adgh",       R8A779A0_CLK_ADGH,      CLK_PLL5_DIV4,  1, 1),
@@ -116,15 +109,22 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = {
        DEF_FIXED("vcbus",      R8A779A0_CLK_VCBUS,     CLK_PLL5_DIV4,  1, 1),
        DEF_FIXED("cbfusa",     R8A779A0_CLK_CBFUSA,    CLK_EXTAL,      2, 1),
        DEF_FIXED("cp",         R8A779A0_CLK_CP,        CLK_EXTAL,      2, 1),
+       DEF_FIXED("cl16mck",    R8A779A0_CLK_CL16MCK,   CLK_PLL1_DIV2,  64, 1),
+
+       DEF_GEN4_SDH("sd0h",    R8A779A0_CLK_SD0H,      CLK_SDSRC,         0x870),
+       DEF_GEN4_SD("sd0",      R8A779A0_CLK_SD0,       R8A779A0_CLK_SD0H, 0x870),
 
-       DEF_SD("sd0",           R8A779A0_CLK_SD0,       CLK_SDSRC,      0x870),
+       DEF_BASE("rpc",         R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC),
+       DEF_BASE("rpcd2",       R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2,
+                R8A779A0_CLK_RPC),
 
        DEF_DIV6P1("mso",       R8A779A0_CLK_MSO,       CLK_PLL5_DIV4,  0x87c),
        DEF_DIV6P1("canfd",     R8A779A0_CLK_CANFD,     CLK_PLL5_DIV4,  0x878),
        DEF_DIV6P1("csi0",      R8A779A0_CLK_CSI0,      CLK_PLL5_DIV4,  0x880),
+       DEF_DIV6P1("dsi",       R8A779A0_CLK_DSI,       CLK_PLL5_DIV4,  0x884),
 
-       DEF_OSC("osc",          R8A779A0_CLK_OSC,       CLK_EXTAL,      8),
-       DEF_MDSEL("r",          R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
+       DEF_GEN4_OSC("osc",     R8A779A0_CLK_OSC,       CLK_EXTAL,      8),
+       DEF_GEN4_MDSEL("r",     R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
 };
 
 static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
@@ -134,10 +134,14 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
        DEF_MOD("avb3",         214,    R8A779A0_CLK_S3D2),
        DEF_MOD("avb4",         215,    R8A779A0_CLK_S3D2),
        DEF_MOD("avb5",         216,    R8A779A0_CLK_S3D2),
+       DEF_MOD("canfd0",       328,    R8A779A0_CLK_CANFD),
        DEF_MOD("csi40",        331,    R8A779A0_CLK_CSI0),
        DEF_MOD("csi41",        400,    R8A779A0_CLK_CSI0),
        DEF_MOD("csi42",        401,    R8A779A0_CLK_CSI0),
        DEF_MOD("csi43",        402,    R8A779A0_CLK_CSI0),
+       DEF_MOD("du",           411,    R8A779A0_CLK_S3D1),
+       DEF_MOD("dsi0",         415,    R8A779A0_CLK_DSI),
+       DEF_MOD("dsi1",         416,    R8A779A0_CLK_DSI),
        DEF_MOD("fcpvd0",       508,    R8A779A0_CLK_S3D1),
        DEF_MOD("fcpvd1",       509,    R8A779A0_CLK_S3D1),
        DEF_MOD("hscif0",       514,    R8A779A0_CLK_S1D2),
@@ -151,12 +155,17 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
        DEF_MOD("i2c4",         522,    R8A779A0_CLK_S1D4),
        DEF_MOD("i2c5",         523,    R8A779A0_CLK_S1D4),
        DEF_MOD("i2c6",         524,    R8A779A0_CLK_S1D4),
+       DEF_MOD("ispcs0",       612,    R8A779A0_CLK_S1D1),
+       DEF_MOD("ispcs1",       613,    R8A779A0_CLK_S1D1),
+       DEF_MOD("ispcs2",       614,    R8A779A0_CLK_S1D1),
+       DEF_MOD("ispcs3",       615,    R8A779A0_CLK_S1D1),
        DEF_MOD("msi0",         618,    R8A779A0_CLK_MSO),
        DEF_MOD("msi1",         619,    R8A779A0_CLK_MSO),
        DEF_MOD("msi2",         620,    R8A779A0_CLK_MSO),
        DEF_MOD("msi3",         621,    R8A779A0_CLK_MSO),
        DEF_MOD("msi4",         622,    R8A779A0_CLK_MSO),
        DEF_MOD("msi5",         623,    R8A779A0_CLK_MSO),
+       DEF_MOD("rpc-if",       629,    R8A779A0_CLK_RPCD2),
        DEF_MOD("scif0",        702,    R8A779A0_CLK_S1D8),
        DEF_MOD("scif1",        703,    R8A779A0_CLK_S1D8),
        DEF_MOD("scif3",        704,    R8A779A0_CLK_S1D8),
@@ -164,6 +173,12 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
        DEF_MOD("sdhi0",        706,    R8A779A0_CLK_SD0),
        DEF_MOD("sydm1",        709,    R8A779A0_CLK_S1D2),
        DEF_MOD("sydm2",        710,    R8A779A0_CLK_S1D2),
+       DEF_MOD("tmu0",         713,    R8A779A0_CLK_CL16MCK),
+       DEF_MOD("tmu1",         714,    R8A779A0_CLK_S1D4),
+       DEF_MOD("tmu2",         715,    R8A779A0_CLK_S1D4),
+       DEF_MOD("tmu3",         716,    R8A779A0_CLK_S1D4),
+       DEF_MOD("tmu4",         717,    R8A779A0_CLK_S1D4),
+       DEF_MOD("tpu0",         718,    R8A779A0_CLK_S1D8),
        DEF_MOD("vin00",        730,    R8A779A0_CLK_S1D1),
        DEF_MOD("vin01",        731,    R8A779A0_CLK_S1D1),
        DEF_MOD("vin02",        800,    R8A779A0_CLK_S1D1),
@@ -199,10 +214,15 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
        DEF_MOD("vspd0",        830,    R8A779A0_CLK_S3D1),
        DEF_MOD("vspd1",        831,    R8A779A0_CLK_S3D1),
        DEF_MOD("rwdt",         907,    R8A779A0_CLK_R),
+       DEF_MOD("cmt0",         910,    R8A779A0_CLK_R),
+       DEF_MOD("cmt1",         911,    R8A779A0_CLK_R),
+       DEF_MOD("cmt2",         912,    R8A779A0_CLK_R),
+       DEF_MOD("cmt3",         913,    R8A779A0_CLK_R),
        DEF_MOD("pfc0",         915,    R8A779A0_CLK_CP),
        DEF_MOD("pfc1",         916,    R8A779A0_CLK_CP),
        DEF_MOD("pfc2",         917,    R8A779A0_CLK_CP),
        DEF_MOD("pfc3",         918,    R8A779A0_CLK_CP),
+       DEF_MOD("tsc",          919,    R8A779A0_CLK_CL16MCK),
        DEF_MOD("vspx0",        1028,   R8A779A0_CLK_S1D1),
        DEF_MOD("vspx1",        1029,   R8A779A0_CLK_S1D1),
        DEF_MOD("vspx2",        1030,   R8A779A0_CLK_S1D1),

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 9159071a2b5e9b41b43f1db2a231ea87d2b4efca..85bfc7233b77a87a3122a86e96e33c04054fa1af 100644 (file)
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -30,13 +30,18 @@ enum rcar_gen3_clk_types {
        CLK_TYPE_GEN3_RPC,
        CLK_TYPE_GEN3_RPCD2,
 
-       CLK_TYPE_R8A779A0_MAIN,
-       CLK_TYPE_R8A779A0_PLL1,
-       CLK_TYPE_R8A779A0_PLL2X_3X,     /* PLL[23][01] */
-       CLK_TYPE_R8A779A0_PLL5,
-       CLK_TYPE_R8A779A0_SD,
-       CLK_TYPE_R8A779A0_MDSEL,        /* Select parent/divider using mode pin */
-       CLK_TYPE_R8A779A0_OSC,  /* OSC EXTAL predivider and fixed divider */
+       CLK_TYPE_GEN4_MAIN,
+       CLK_TYPE_GEN4_PLL1,
+       CLK_TYPE_GEN4_PLL2X_3X, /* PLL[23][01] */
+       CLK_TYPE_GEN4_PLL5,
+       CLK_TYPE_GEN4_SDH,
+       CLK_TYPE_GEN4_SD,
+       CLK_TYPE_GEN4_MDSEL,    /* Select parent/divider using mode pin */
+       CLK_TYPE_GEN4_Z,
+       CLK_TYPE_GEN4_OSC,      /* OSC EXTAL predivider and fixed divider */
+       CLK_TYPE_GEN4_RPCSRC,
+       CLK_TYPE_GEN4_RPC,
+       CLK_TYPE_GEN4_RPCD2,
 
        /* SoC specific definitions start here */
        CLK_TYPE_GEN3_SOC_BASE,
@@ -79,6 +84,23 @@ enum rcar_gen3_clk_types {
        DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC,   \
                 (_parent0) << 16 | (_parent1), .div = 8)
 
+#define DEF_GEN4_SDH(_name, _id, _parent, _offset)     \
+       DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
+
+#define DEF_GEN4_SD(_name, _id, _parent, _offset)      \
+       DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
+
+#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
+       DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL,       \
+                (_parent0) << 16 | (_parent1),         \
+                .div = (_div0) << 16 | (_div1), .offset = _md)
+
+#define DEF_GEN4_OSC(_name, _id, _parent, _div)                \
+       DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
+
+#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset)  \
+       DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
+
 struct rcar_gen3_cpg_pll_config {
        u8 extal_div;
        u8 pll1_mult;