85xx: Use BR_ADDR macro for NAND chipselects

Use the new BR_ADDR macro to properly setup the address field of the
localbus chipselects used by NAND.

This allows us to deal with 36-bit phys on these boards in the future.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 63a0f7e675c4558c7308c0bc1ef4cae55fc51d53..1898e265c99a65426c572265161dfaeda1c2b97d 100644 (file)
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -256,7 +256,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
 
 /* NAND flash config */
-#define CONFIG_NAND_BR_PRELIM  (CONFIG_SYS_NAND_BASE_PHYS \
+#define CONFIG_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8              /* Port Size = 8 bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
@@ -273,20 +273,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 #define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 
-#define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\
+#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8              /* Port Size = 8 bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
                                | BR_V)                 /* valid */
 #define CONFIG_SYS_OR4_PRELIM  CONFIG_NAND_OR_PRELIM     /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
+#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8              /* Port Size = 8 bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
                                | BR_V)                 /* valid */
 #define CONFIG_SYS_OR5_PRELIM  CONFIG_NAND_OR_PRELIM     /* NAND Options */
 
-#define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\
+#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8              /* Port Size = 8 bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \

diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 0277a42a243bb4283d7216ea5a5dc2d22493a9cd..332a0e3378433676d9f34e23db5dcabc9726cacd 100644 (file)
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -275,7 +275,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 
 /* NAND flash config */
-#define CONFIG_NAND_BR_PRELIM  (CONFIG_SYS_NAND_BASE_PHYS \
+#define CONFIG_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                               | BR_PS_8               /* Port Size = 8 bit */ \
                               | BR_MS_FCM             /* MSEL = FCM */ \
@@ -292,20 +292,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
 #define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
 
-#define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\
+#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                               | BR_PS_8               /* Port Size = 8 bit */ \
                               | BR_MS_FCM             /* MSEL = FCM */ \
                               | BR_V)                 /* valid */
 #define CONFIG_SYS_OR4_PRELIM  CONFIG_NAND_OR_PRELIM    /* NAND Options */
-#define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
+#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                               | BR_PS_8               /* Port Size = 8 bit */ \
                               | BR_MS_FCM             /* MSEL = FCM */ \
                               | BR_V)                 /* valid */
 #define CONFIG_SYS_OR5_PRELIM  CONFIG_NAND_OR_PRELIM    /* NAND Options */
 
-#define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\
+#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                               | BR_PS_8               /* Port Size = 8 bit */ \
                               | BR_MS_FCM             /* MSEL = FCM */ \