ARM: dts: k3-j721s2: Correct timer frequency

MCU Timer0 runs at 250MHz, and the clock-frequency defined in DT appears
incorrect.

Without this delays in R5 SPL are 10x off.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
index 749bc717f39070c4a084780b3843d6dc248ae406..a17e61eccf2396b3ddbe7dc25c50191f0a8c5917 100644 (file)
--- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
@@ -40,7 +40,7 @@
                compatible = "ti,omap5430-timer";
                reg = <0x0 0x40400000 0x0 0x80>;
                ti,timer-alwon;
-               clock-frequency = <25000000>;
+               clock-frequency = <250000000>;
                u-boot,dm-spl;
        };