*/
#include <common.h>
+#include <netdev.h>
int board_early_init_f (void)
{
{
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
int board_early_init_f (void)
{
{
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
int checkboard (void)
{
{
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
-#ifdef CONFIG_PCI
#include <netdev.h>
-#endif
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
-#ifdef CONFIG_PCI
+#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
- return pci_eth_init(bis);
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_PCI
+ rc += pci_eth_init(bis);
+#endif
+ return rc;
}
#endif
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
{
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include "psd4256.h"
#include "flash-defines.h"
return 0;
}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include "bf533-stamp.h"
}
#endif
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <config.h>
#include <asm/blackfin.h>
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
SSYNC();
}
#endif
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
return gd->bd->bi_memsize;
}
+
+#ifdef CONFIG_SMC91111
+int board_eth_init(bd_t *bis)
+{
+ return smc91111_initialize(0, CONFIG_SMC91111_BASE);
+}
+#endif
#include <asm/arch/pxa-regs.h>
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
PHYS_SDRAM_3_SIZE +
PHYS_SDRAM_4_SIZE );
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <i2c.h>
#include <da9030.h>
#include <malloc.h>
i2c_reg_write(addr, SYS_CONTROL_A, val);
}
#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <SA-1100.h>
DECLARE_GLOBAL_DATA_PTR;
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <config.h>
#include <asm/leon.h>
{
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <config.h>
#include <asm/leon.h>
{
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <asm/arch/pxa-regs.h>
#include <asm/mach-types.h>
return;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <asm/arch/pxa-regs.h>
DECLARE_GLOBAL_DATA_PTR;
return;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#if defined(CONFIG_LH7A400)
#include <lh7a400.h>
#elif defined(CONFIG_LH7A404)
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
{
writew(value & 0xFF, LED_BASE);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
#include <common.h>
#include <exports.h>
#include <timestamp.h>
+#include <net.h>
#include "../drivers/net/smc91111.h"
-#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
-
-static u16 read_eeprom_reg(u16 reg)
+static u16 read_eeprom_reg(struct eth_device *dev, u16 reg)
{
int timeout;
- SMC_SELECT_BANK(2);
- SMC_outw(reg, PTR_REG);
+ SMC_SELECT_BANK(dev, 2);
+ SMC_outw(dev, reg, PTR_REG);
- SMC_SELECT_BANK(1);
- SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
+ SMC_SELECT_BANK(dev, 1);
+ SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
CTL_REG);
timeout = 100;
- while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout)
+ while((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
udelay(100);
if (timeout == 0) {
printf("Timeout Reading EEPROM register %02x\n", reg);
return 0;
}
- return SMC_inw (GP_REG);
+ return SMC_inw (dev, GP_REG);
}
-static int write_eeprom_reg(u16 value, u16 reg)
+static int write_eeprom_reg(struct eth_device *dev, u16 value, u16 reg)
{
int timeout;
- SMC_SELECT_BANK(2);
- SMC_outw(reg, PTR_REG);
+ SMC_SELECT_BANK(dev, 2);
+ SMC_outw(dev, reg, PTR_REG);
- SMC_SELECT_BANK(1);
- SMC_outw(value, GP_REG);
- SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
+ SMC_SELECT_BANK(dev, 1);
+ SMC_outw(dev, value, GP_REG);
+ SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
timeout = 100;
- while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout)
+ while ((SMC_inw(dev, CTL_REG) & CTL_STORE) && --timeout)
udelay (100);
if (timeout == 0) {
printf("Timeout Writing EEPROM register %02x\n", reg);
return 1;
}
-static int write_data(u16 *buf, int len)
+static int write_data(struct eth_device *dev, u16 *buf, int len)
{
u16 reg = 0x23;
while (len--)
- write_eeprom_reg(*buf++, reg++);
+ write_eeprom_reg(dev, *buf++, reg++);
return 0;
}
-static int verify_macaddr(char *s)
+static int verify_macaddr(struct eth_device *dev, char *s)
{
u16 reg;
int i, err = 0;
printf("MAC Address: ");
err = i = 0;
for (i = 0; i < 3; i++) {
- reg = read_eeprom_reg(0x20 + i);
+ reg = read_eeprom_reg(dev, 0x20 + i);
printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
if (s)
err |= reg != ((u16 *)s)[i];
return err ? 0 : 1;
}
-static int set_mac(char *s)
+static int set_mac(struct eth_device *dev, char *s)
{
int i;
char *e, eaddr[6];
}
for (i = 0; i < 3; i++)
- write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
+ write_eeprom_reg(dev, *(((u16 *)eaddr) + i), 0x20 + i);
return 0;
}
int i, len, ret;
unsigned char buf[58], *p;
+ struct eth_device dev = {
+ .iobase = CONFIG_SMC91111_BASE
+ };
+
app_startup(argv);
if (get_version() != XF_VERSION) {
printf("Wrong XF_VERSION.\n");
return crcek();
- if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
+ if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
printf("SMSC91111 not found.\n");
return 2;
}
/* Called without parameters - print MAC address */
if (argc < 2) {
- verify_macaddr(NULL);
+ verify_macaddr(&dev, NULL);
return 0;
}
}
/* First argument (MAC) is mandatory */
- set_mac(argv[1]);
- if (verify_macaddr(argv[1])) {
+ set_mac(&dev, argv[1]);
+ if (verify_macaddr(&dev, argv[1])) {
printf("*** MAC address does not match! ***\n");
return 4;
}
while (len--)
*p++ = 0;
- write_data((u16 *)buf, sizeof(buf) >> 1);
+ write_data(&dev, (u16 *)buf, sizeof(buf) >> 1);
return 0;
}
*/
#include <common.h>
+#include <netdev.h>
#include <i2c.h>
#include <flash.h>
#include <nand.h>
return 0;
}
#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
int board_early_init_f (void)
{
{
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
);
#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/processor.h>
void led_set_state (unsigned short value)
{
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
#include <common.h>
#include <exports.h>
#include <timestamp.h>
+#include <net.h>
#include "../drivers/net/smc91111.h"
-#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
-
-static u16 read_eeprom_reg(u16 reg)
+static u16 read_eeprom_reg(struct eth_device *dev, u16 reg)
{
int timeout;
- SMC_SELECT_BANK(2);
- SMC_outw(reg, PTR_REG);
+ SMC_SELECT_BANK(dev, 2);
+ SMC_outw(dev, reg, PTR_REG);
- SMC_SELECT_BANK(1);
- SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
+ SMC_SELECT_BANK(dev, 1);
+ SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
CTL_REG);
timeout = 100;
- while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout)
+ while((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
udelay(100);
if (timeout == 0) {
printf("Timeout Reading EEPROM register %02x\n", reg);
return 0;
}
- return SMC_inw (GP_REG);
+ return SMC_inw (dev, GP_REG);
}
-static int write_eeprom_reg(u16 value, u16 reg)
+static int write_eeprom_reg(struct eth_device *dev, u16 value, u16 reg)
{
int timeout;
- SMC_SELECT_BANK(2);
- SMC_outw(reg, PTR_REG);
+ SMC_SELECT_BANK(dev, 2);
+ SMC_outw(dev, reg, PTR_REG);
- SMC_SELECT_BANK(1);
- SMC_outw(value, GP_REG);
- SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
+ SMC_SELECT_BANK(dev, 1);
+ SMC_outw(dev, value, GP_REG);
+ SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
timeout = 100;
- while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout)
+ while ((SMC_inw(dev, CTL_REG) & CTL_STORE) && --timeout)
udelay (100);
if (timeout == 0) {
printf("Timeout Writing EEPROM register %02x\n", reg);
return 1;
}
-static int write_data(u16 *buf, int len)
+static int write_data(struct eth_device *dev, u16 *buf, int len)
{
u16 reg = 0x23;
while (len--)
- write_eeprom_reg(*buf++, reg++);
+ write_eeprom_reg(dev, *buf++, reg++);
return 0;
}
-static int verify_macaddr(char *s)
+static int verify_macaddr(struct eth_device *dev, char *s)
{
u16 reg;
int i, err = 0;
printf("MAC Address: ");
err = i = 0;
for (i = 0; i < 3; i++) {
- reg = read_eeprom_reg(0x20 + i);
+ reg = read_eeprom_reg(dev, 0x20 + i);
printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
if (s)
err |= reg != ((u16 *)s)[i];
return err ? 0 : 1;
}
-static int set_mac(char *s)
+static int set_mac(struct eth_device *dev, char *s)
{
int i;
char *e, eaddr[6];
}
for (i = 0; i < 3; i++)
- write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
+ write_eeprom_reg(dev, *(((u16 *)eaddr) + i), 0x20 + i);
return 0;
}
int i, len, ret;
unsigned char buf[58], *p;
+ struct eth_device dev = {
+ .iobase = CONFIG_SMC91111_BASE
+ };
+
app_startup(argv);
if (get_version() != XF_VERSION) {
printf("Wrong XF_VERSION.\n");
return 1;
}
- if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
+ if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
printf("SMSC91111 not found.\n");
return 2;
}
/* Called without parameters - print MAC address */
if (argc < 2) {
- verify_macaddr(NULL);
+ verify_macaddr(&dev, NULL);
return 0;
}
}
/* First argument (MAC) is mandatory */
- set_mac(argv[1]);
- if (verify_macaddr(argv[1])) {
+ set_mac(&dev, argv[1]);
+ if (verify_macaddr(&dev, argv[1])) {
printf("*** MAC address does not match! ***\n");
return 4;
}
while (len--)
*p++ = 0;
- write_data((u16 *)buf, sizeof(buf) >> 1);
+ write_data(&dev, (u16 *)buf, sizeof(buf) >> 1);
return 0;
}
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
#include <asm/arch/pxa-regs.h>
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
return (0);
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
*/
#include <common.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+ return rc;
+}
+#endif
COBJS-$(CONFIG_RTL8169) += rtl8169.o
COBJS-$(CONFIG_DRIVER_S3C4510_ETH) += s3c4510b_eth.o
COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
-COBJS-$(CONFIG_DRIVER_SMC91111) += smc91111.o
+COBJS-$(CONFIG_SMC91111) += smc91111.o
COBJS-$(CONFIG_SMC911X) += smc911x.o
COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
#include <common.h>
#include <command.h>
#include <config.h>
+#include <malloc.h>
#include "smc91111.h"
#include <net.h>
. what you are doing.
.
-------------------------------------------------------------------------*/
-#define CARDNAME "LAN91C111"
/* Memory sizing constant */
#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
#ifndef CONFIG_SMC91111_BASE
-#define CONFIG_SMC91111_BASE 0x20000300
+#error "SMC91111 Base address must be passed to initialization funciton"
+/* #define CONFIG_SMC91111_BASE 0x20000300 */
#endif
-#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
-
#define SMC_DEV_NAME "SMC91111"
#define SMC_PHY_ADDR 0x0000
#define SMC_ALLOC_MAX_TRY 5
#else
#undef USE_32_BIT
#endif
-/*-----------------------------------------------------------------
- .
- . The driver can be entered at any of the following entry points.
- .
- .------------------------------------------------------------------ */
-
-extern int eth_init(bd_t *bd);
-extern void eth_halt(void);
-extern int eth_rx(void);
-extern int eth_send(volatile void *packet, int length);
#ifdef SHARED_RESOURCES
- extern void swap_to(int device_id);
+extern void swap_to(int device_id);
+#else
+# define swap_to(x)
#endif
-/*
- . This is called by register_netdev(). It is responsible for
- . checking the portlist for the SMC9000 series chipset. If it finds
- . one, then it will initialize the device, find the hardware information,
- . and sets up the appropriate device parameters.
- . NOTE: Interrupts are *OFF* when this procedure is called.
- .
- . NB:This shouldn't be static since it is referred to externally.
-*/
-int smc_init(void);
-
-/*
- . This is called by unregister_netdev(). It is responsible for
- . cleaning up before the driver is finally unregistered and discarded.
-*/
-void smc_destructor(void);
-
-/*
- . The kernel calls this function when someone wants to use the device,
- . typically 'ifconfig ethX up'.
-*/
-static int smc_open(bd_t *bd);
-
-
-/*
- . This is called by the kernel in response to 'ifconfig ethX down'. It
- . is responsible for cleaning up everything that the open routine
- . does, and maybe putting the card into a powerdown state.
-*/
-static int smc_close(void);
-
-/*
- . Configures the PHY through the MII Management interface
-*/
#ifndef CONFIG_SMC91111_EXT_PHY
-static void smc_phy_configure(void);
+static void smc_phy_configure(struct eth_device *dev);
#endif /* !CONFIG_SMC91111_EXT_PHY */
-/*
- . This is a separate procedure to handle the receipt of a packet, to
- . leave the interrupt code looking slightly cleaner
-*/
-static int smc_rcv(void);
-
-/* See if a MAC address is defined in the current environment. If so use it. If not
- . print a warning and set the environment and other globals with the default.
- . If an EEPROM is present it really should be consulted.
-*/
-int smc_get_ethaddr(bd_t *bd);
-int get_rom_mac(uchar *v_rom_mac);
-
/*
------------------------------------------------------------
.
* packets being corrupt (shifted) on the wire, etc. Switching to the
* inx,outx functions fixed this problem.
*/
-static inline word SMC_inw(dword offset);
-static inline void SMC_outw(word value, dword offset);
-static inline byte SMC_inb(dword offset);
-static inline void SMC_outb(byte value, dword offset);
-static inline void SMC_insw(dword offset, volatile uchar* buf, dword len);
-static inline void SMC_outsw(dword offset, uchar* buf, dword len);
#define barrier() __asm__ __volatile__("": : :"memory")
-static inline word SMC_inw(dword offset)
+static inline word SMC_inw(struct eth_device *dev, dword offset)
{
word v;
- v = *((volatile word*)(SMC_BASE_ADDRESS+offset));
+ v = *((volatile word*)(dev->iobase + offset));
barrier(); *(volatile u32*)(0xc0000000);
return v;
}
-static inline void SMC_outw(word value, dword offset)
+static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
{
- *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value;
+ *((volatile word*)(dev->iobase + offset)) = value;
barrier(); *(volatile u32*)(0xc0000000);
}
-static inline byte SMC_inb(dword offset)
+static inline byte SMC_inb(struct eth_device *dev, dword offset)
{
word _w;
- _w = SMC_inw(offset & ~((dword)1));
+ _w = SMC_inw(dev, offset & ~((dword)1));
return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
}
-static inline void SMC_outb(byte value, dword offset)
+static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
{
word _w;
- _w = SMC_inw(offset & ~((dword)1));
+ _w = SMC_inw(dev, offset & ~((dword)1));
if (offset & 1)
- *((volatile word*)(SMC_BASE_ADDRESS+(offset & ~((dword)1)))) = (value<<8) | (_w & 0x00ff);
+ *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
+ (value<<8) | (_w & 0x00ff);
else
- *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value | (_w & 0xff00);
+ *((volatile word*)(dev->iobase + offset)) =
+ value | (_w & 0xff00);
}
-static inline void SMC_insw(dword offset, volatile uchar* buf, dword len)
+static inline void SMC_insw(struct eth_device *dev, dword offset,
+ volatile uchar* buf, dword len)
{
volatile word *p = (volatile word *)buf;
while (len-- > 0) {
- *p++ = SMC_inw(offset);
+ *p++ = SMC_inw(dev, offset);
barrier();
*((volatile u32*)(0xc0000000));
}
}
-static inline void SMC_outsw(dword offset, uchar* buf, dword len)
+static inline void SMC_outsw(struct eth_device *dev, dword offset,
+ uchar* buf, dword len)
{
volatile word *p = (volatile word *)buf;
while (len-- > 0) {
- SMC_outw(*p++, offset);
+ SMC_outw(dev, *p++, offset);
barrier();
*(volatile u32*)(0xc0000000);
}
}
#endif /* CONFIG_SMC_USE_IOFUNCS */
-static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
-
-/*
- * This function must be called before smc_open() if you want to override
- * the default mac address.
- */
-
-void smc_set_mac_addr(const unsigned char *addr) {
- int i;
-
- for (i=0; i < sizeof(smc_mac_addr); i++){
- smc_mac_addr[i] = addr[i];
- }
-}
-
-/*
- * smc_get_macaddr is no longer used. If you want to override the default
- * mac address, call smc_get_mac_addr as a part of the board initialization.
- */
-
-#if 0
-void smc_get_macaddr( byte *addr ) {
- /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
- unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
- int i;
-
-
- for (i=0; i<6; i++) {
- addr[0] = *(dnp1110_mac+0);
- addr[1] = *(dnp1110_mac+1);
- addr[2] = *(dnp1110_mac+2);
- addr[3] = *(dnp1110_mac+3);
- addr[4] = *(dnp1110_mac+4);
- addr[5] = *(dnp1110_mac+5);
- }
-}
-#endif /* 0 */
-
-/***********************************************
- * Show available memory *
- ***********************************************/
-void dump_memory_info(void)
-{
- word mem_info;
- word old_bank;
-
- old_bank = SMC_inw(BANK_SELECT)&0xF;
-
- SMC_SELECT_BANK(0);
- mem_info = SMC_inw( MIR_REG );
- PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
-
- SMC_SELECT_BANK(old_bank);
-}
/*
. A rather simple routine to print out a packet for debugging purposes.
*/
#define tx_done(dev) 1
-
-/* this does a soft reset on the device */
-static void smc_reset( void );
-
-/* Enable Interrupts, Receive, and Transmit */
-static void smc_enable( void );
-
-/* this puts the device in an inactive state */
-static void smc_shutdown( void );
-
-/* Routines to Read and Write the PHY Registers across the
- MII Management Interface
-*/
-
-#ifndef CONFIG_SMC91111_EXT_PHY
-static word smc_read_phy_register(byte phyreg);
-static void smc_write_phy_register(byte phyreg, word phydata);
-#endif /* !CONFIG_SMC91111_EXT_PHY */
-
-
-static int poll4int (byte mask, int timeout)
+static int poll4int (struct eth_device *dev, byte mask, int timeout)
{
int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
int is_timeout = 0;
- word old_bank = SMC_inw (BSR_REG);
+ word old_bank = SMC_inw (dev, BSR_REG);
PRINTK2 ("Polling...\n");
- SMC_SELECT_BANK (2);
- while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) {
+ SMC_SELECT_BANK (dev, 2);
+ while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
if (get_timer (0) >= tmo) {
is_timeout = 1;
break;
}
/* restore old bank selection */
- SMC_SELECT_BANK (old_bank);
+ SMC_SELECT_BANK (dev, old_bank);
if (is_timeout)
return 1;
}
/* Only one release command at a time, please */
-static inline void smc_wait_mmu_release_complete (void)
+static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
{
int count = 0;
/* assume bank 2 selected */
- while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
+ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
udelay (1); /* Wait until not busy */
if (++count > 200)
break;
. 5. clear all interrupts
.
*/
-static void smc_reset (void)
+static void smc_reset (struct eth_device *dev)
{
PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
/* This resets the registers mostly to defaults, but doesn't
affect EEPROM. That seems unnecessary */
- SMC_SELECT_BANK (0);
- SMC_outw (RCR_SOFTRST, RCR_REG);
+ SMC_SELECT_BANK (dev, 0);
+ SMC_outw (dev, RCR_SOFTRST, RCR_REG);
/* Setup the Configuration Register */
/* This is necessary because the CONFIG_REG is not affected */
/* by a soft reset */
- SMC_SELECT_BANK (1);
+ SMC_SELECT_BANK (dev, 1);
#if defined(CONFIG_SMC91111_EXT_PHY)
- SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
+ SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
#else
- SMC_outw (CONFIG_DEFAULT, CONFIG_REG);
+ SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
#endif
/* Release from possible power-down state */
/* Configuration register is not affected by Soft Reset */
- SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG);
+ SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
+ CONFIG_REG);
- SMC_SELECT_BANK (0);
+ SMC_SELECT_BANK (dev, 0);
/* this should pause enough for the chip to be happy */
udelay (10);
/* Disable transmit and receive functionality */
- SMC_outw (RCR_CLEAR, RCR_REG);
- SMC_outw (TCR_CLEAR, TCR_REG);
+ SMC_outw (dev, RCR_CLEAR, RCR_REG);
+ SMC_outw (dev, TCR_CLEAR, TCR_REG);
/* set the control register */
- SMC_SELECT_BANK (1);
- SMC_outw (CTL_DEFAULT, CTL_REG);
+ SMC_SELECT_BANK (dev, 1);
+ SMC_outw (dev, CTL_DEFAULT, CTL_REG);
/* Reset the MMU */
- SMC_SELECT_BANK (2);
- smc_wait_mmu_release_complete ();
- SMC_outw (MC_RESET, MMU_CMD_REG);
- while (SMC_inw (MMU_CMD_REG) & MC_BUSY)
+ SMC_SELECT_BANK (dev, 2);
+ smc_wait_mmu_release_complete (dev);
+ SMC_outw (dev, MC_RESET, MMU_CMD_REG);
+ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
udelay (1); /* Wait until not busy */
/* Note: It doesn't seem that waiting for the MMU busy is needed here,
of issuing another MMU command right after this */
/* Disable all interrupts */
- SMC_outb (0, IM_REG);
+ SMC_outb (dev, 0, IM_REG);
}
/*
. 2. Enable the receiver
. 3. Enable interrupts
*/
-static void smc_enable()
+static void smc_enable(struct eth_device *dev)
{
PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
- SMC_SELECT_BANK( 0 );
+ SMC_SELECT_BANK( dev, 0 );
/* see the header file for options in TCR/RCR DEFAULT*/
- SMC_outw( TCR_DEFAULT, TCR_REG );
- SMC_outw( RCR_DEFAULT, RCR_REG );
+ SMC_outw( dev, TCR_DEFAULT, TCR_REG );
+ SMC_outw( dev, RCR_DEFAULT, RCR_REG );
/* clear MII_DIS */
/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
}
/*
- . Function: smc_shutdown
+ . Function: smc_halt
. Purpose: closes down the SMC91xxx chip.
. Method:
. 1. zero the interrupt mask
. the manual says that it will wake up in response to any I/O requests
. in the register space. Empirical results do not show this working.
*/
-static void smc_shutdown()
+static void smc_halt(struct eth_device *dev)
{
- PRINTK2(CARDNAME ": smc_shutdown\n");
+ PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
/* no more interrupts for me */
- SMC_SELECT_BANK( 2 );
- SMC_outb( 0, IM_REG );
+ SMC_SELECT_BANK( dev, 2 );
+ SMC_outb( dev, 0, IM_REG );
/* and tell the card to stay away from that nasty outside world */
- SMC_SELECT_BANK( 0 );
- SMC_outb( RCR_CLEAR, RCR_REG );
- SMC_outb( TCR_CLEAR, TCR_REG );
-#ifdef SHARED_RESOURCES
+ SMC_SELECT_BANK( dev, 0 );
+ SMC_outb( dev, RCR_CLEAR, RCR_REG );
+ SMC_outb( dev, TCR_CLEAR, TCR_REG );
+
swap_to(FLASH);
-#endif
}
/*
- . Function: smc_hardware_send_packet(struct net_device * )
+ . Function: smc_send(struct net_device * )
. Purpose:
. This sends the actual packet to the SMC9xxx chip.
.
. Enable the transmit interrupt, so I know if it failed
. Free the kernel data if I actually sent it.
*/
-static int smc_send_packet (volatile void *packet, int packet_length)
+static int smc_send(struct eth_device *dev, volatile void *packet,
+ int packet_length)
{
byte packet_no;
- unsigned long ioaddr;
byte *buf;
int length;
int numPages;
word saved_ptr;
/* save PTR and PNR registers before manipulation */
- SMC_SELECT_BANK (2);
- saved_pnr = SMC_inb( PN_REG );
- saved_ptr = SMC_inw( PTR_REG );
+ SMC_SELECT_BANK (dev, 2);
+ saved_pnr = SMC_inb( dev, PN_REG );
+ saved_ptr = SMC_inw( dev, PTR_REG );
PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
}
/* now, try to allocate the memory */
- SMC_SELECT_BANK (2);
- SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG);
+ SMC_SELECT_BANK (dev, 2);
+ SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
/* FIXME: the ALLOC_INT bit never gets set *
* so the following will always give a *
try++;
time_out = MEMORY_WAIT_TIME;
do {
- status = SMC_inb (SMC91111_INT_REG);
+ status = SMC_inb (dev, SMC91111_INT_REG);
if (status & IM_ALLOC_INT) {
/* acknowledge the interrupt */
- SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG);
+ SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
break;
}
} while (--time_out);
PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
SMC_DEV_NAME, try);
- /* I can send the packet now.. */
-
- ioaddr = SMC_BASE_ADDRESS;
-
buf = (byte *) packet;
/* If I get here, I _know_ there is a packet slot waiting for me */
- packet_no = SMC_inb (AR_REG);
+ packet_no = SMC_inb (dev, AR_REG);
if (packet_no & AR_FAILED) {
/* or isn't there? BAD CHIP! */
printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
/* we have a packet address, so tell the card to use it */
#ifndef CONFIG_XAENIAX
- SMC_outb (packet_no, PN_REG);
+ SMC_outb (dev, packet_no, PN_REG);
#else
/* On Xaeniax board, we can't use SMC_outb here because that way
* the Allocate MMU command will end up written to the command register
* as well, which will lead to a problem.
*/
- SMC_outl (packet_no << 16, 0);
+ SMC_outl (dev, packet_no << 16, 0);
#endif
/* do not write new ptr value if Write data fifo not empty */
while ( saved_ptr & PTR_NOTEMPTY )
printf ("Write data fifo not empty!\n");
/* point to the beginning of the packet */
- SMC_outw (PTR_AUTOINC, PTR_REG);
+ SMC_outw (dev, PTR_AUTOINC, PTR_REG);
PRINTK3 ("%s: Trying to xmit packet of length %x\n",
SMC_DEV_NAME, length);
/* send the packet length ( +6 for status, length and ctl byte )
and the status word ( set to zeros ) */
#ifdef USE_32_BIT
- SMC_outl ((length + 6) << 16, SMC91111_DATA_REG);
+ SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
#else
- SMC_outw (0, SMC91111_DATA_REG);
+ SMC_outw (dev, 0, SMC91111_DATA_REG);
/* send the packet length ( +6 for status words, length, and ctl */
- SMC_outw ((length + 6), SMC91111_DATA_REG);
+ SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
#endif
/* send the actual data
. almost as much time as is saved?
*/
#ifdef USE_32_BIT
- SMC_outsl (SMC91111_DATA_REG, buf, length >> 2);
+ SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
#ifndef CONFIG_XAENIAX
if (length & 0x2)
- SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))),
+ SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
SMC91111_DATA_REG);
#else
/* On XANEIAX, we can only use 32-bit writes, so we need to handle
*/
if ((length & 3) == 3) {
u16 * ptr = (u16*) &buf[length-3];
- SMC_outl((*ptr) | ((0x2000 | buf[length-1]) << 16),
+ SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16),
SMC91111_DATA_REG);
} else if ((length & 2) == 2) {
u16 * ptr = (u16*) &buf[length-2];
- SMC_outl(*ptr, SMC91111_DATA_REG);
+ SMC_outl(dev, *ptr, SMC91111_DATA_REG);
} else if (length & 1) {
- SMC_outl((0x2000 | buf[length-1]), SMC91111_DATA_REG);
+ SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG);
} else {
- SMC_outl(0, SMC91111_DATA_REG);
+ SMC_outl(dev, 0, SMC91111_DATA_REG);
}
#endif
#else
- SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1);
+ SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
#endif /* USE_32_BIT */
#ifndef CONFIG_XAENIAX
/* Send the last byte, if there is one. */
if ((length & 1) == 0) {
- SMC_outw (0, SMC91111_DATA_REG);
+ SMC_outw (dev, 0, SMC91111_DATA_REG);
} else {
- SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG);
+ SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
}
#endif
/* and let the chipset deal with it */
- SMC_outw (MC_ENQUEUE, MMU_CMD_REG);
+ SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
/* poll for TX INT */
- /* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */
+ /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
/* poll for TX_EMPTY INT - autorelease enabled */
- if (poll4int(IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
+ if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
/* sending failed */
PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
/* release packet */
/* no need to release, MMU does that now */
#ifdef CONFIG_XAENIAX
- SMC_outw (MC_FREEPKT, MMU_CMD_REG);
+ SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
#endif
/* wait for MMU getting ready (low) */
- while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
+ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
udelay (10);
}
return 0;
} else {
/* ack. int */
- SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG);
+ SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
/* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
length);
/* release packet */
/* no need to release, MMU does that now */
#ifdef CONFIG_XAENIAX
- SMC_outw (MC_FREEPKT, MMU_CMD_REG);
+ SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
#endif
/* wait for MMU getting ready (low) */
- while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
+ while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
udelay (10);
}
/* restore previously saved registers */
#ifndef CONFIG_XAENIAX
- SMC_outb( saved_pnr, PN_REG );
+ SMC_outb( dev, saved_pnr, PN_REG );
#else
/* On Xaeniax board, we can't use SMC_outb here because that way
* the Allocate MMU command will end up written to the command register
* as well, which will lead to a problem.
*/
- SMC_outl(saved_pnr << 16, 0);
+ SMC_outl(dev, saved_pnr << 16, 0);
#endif
- SMC_outw( saved_ptr, PTR_REG );
+ SMC_outw( dev, saved_ptr, PTR_REG );
return length;
}
-/*-------------------------------------------------------------------------
- |
- | smc_destructor( struct net_device * dev )
- | Input parameters:
- | dev, pointer to the device structure
- |
- | Output:
- | None.
- |
- ---------------------------------------------------------------------------
-*/
-void smc_destructor()
-{
- PRINTK2(CARDNAME ": smc_destructor\n");
-}
-
-
/*
* Open and Initialize the board
*
* Set up everything, reset the card, etc ..
*
*/
-static int smc_open (bd_t * bd)
+static int smc_init(struct eth_device *dev, bd_t *bd)
{
- int i, err;
+ int i;
- PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME);
+ swap_to(ETHERNET);
+
+ PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
/* reset the hardware */
- smc_reset ();
- smc_enable ();
+ smc_reset (dev);
+ smc_enable (dev);
/* Configure the PHY */
#ifndef CONFIG_SMC91111_EXT_PHY
- smc_phy_configure ();
+ smc_phy_configure (dev);
#endif
/* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
-/* SMC_SELECT_BANK(0); */
-/* SMC_outw(0, RPC_REG); */
- SMC_SELECT_BANK (1);
+/* SMC_SELECT_BANK(dev, 0); */
+/* SMC_outw(dev, 0, RPC_REG); */
+ SMC_SELECT_BANK (dev, 1);
- err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */
- if (err < 0)
- return -1;
#ifdef USE_32_BIT
for (i = 0; i < 6; i += 2) {
word address;
- address = smc_mac_addr[i + 1] << 8;
- address |= smc_mac_addr[i];
- SMC_outw (address, (ADDR0_REG + i));
+ address = dev->enetaddr[i + 1] << 8;
+ address |= dev->enetaddr[i];
+ SMC_outw(dev, address, (ADDR0_REG + i));
}
#else
for (i = 0; i < 6; i++)
- SMC_outb (smc_mac_addr[i], (ADDR0_REG + i));
+ SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
#endif
+ printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
+
return 0;
}
. o otherwise, read in the packet
--------------------------------------------------------------
*/
-static int smc_rcv()
+static int smc_rcv(struct eth_device *dev)
{
int packet_number;
word status;
byte saved_pnr;
word saved_ptr;
- SMC_SELECT_BANK(2);
+ SMC_SELECT_BANK(dev, 2);
/* save PTR and PTR registers */
- saved_pnr = SMC_inb( PN_REG );
- saved_ptr = SMC_inw( PTR_REG );
+ saved_pnr = SMC_inb( dev, PN_REG );
+ saved_ptr = SMC_inw( dev, PTR_REG );
- packet_number = SMC_inw( RXFIFO_REG );
+ packet_number = SMC_inw( dev, RXFIFO_REG );
if ( packet_number & RXFIFO_REMPTY ) {
PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
/* start reading from the start of the packet */
- SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
+ SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
/* First two words are status and packet_length */
#ifdef USE_32_BIT
- stat_len = SMC_inl(SMC91111_DATA_REG);
+ stat_len = SMC_inl(dev, SMC91111_DATA_REG);
status = stat_len & 0xffff;
packet_length = stat_len >> 16;
#else
- status = SMC_inw( SMC91111_DATA_REG );
- packet_length = SMC_inw( SMC91111_DATA_REG );
+ status = SMC_inw( dev, SMC91111_DATA_REG );
+ packet_length = SMC_inw( dev, SMC91111_DATA_REG );
#endif
packet_length &= 0x07ff; /* mask off top bits */
to send the DWORDs or the bytes first, or some
mixture. A mixture might improve already slow PIO
performance */
- SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
+ SMC_insl( dev, SMC91111_DATA_REG, NetRxPackets[0],
+ packet_length >> 2 );
/* read the left over bytes */
if (packet_length & 3) {
int i;
- byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3));
- dword leftover = SMC_inl(SMC91111_DATA_REG);
+ byte *tail = (byte *)(NetRxPackets[0] +
+ (packet_length & ~3));
+ dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
for (i=0; i<(packet_length & 3); i++)
*tail++ = (byte) (leftover >> (8*i)) & 0xff;
}
#else
PRINTK3(" Reading %d words and %d byte(s) \n",
(packet_length >> 1 ), packet_length & 1 );
- SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1);
+ SMC_insw(dev, SMC91111_DATA_REG , NetRxPackets[0],
+ packet_length >> 1);
#endif /* USE_32_BIT */
is_error = 1;
}
- while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
+ while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
udelay(1); /* Wait until not busy */
/* error or good, tell the card to get rid of this packet */
- SMC_outw( MC_RELEASE, MMU_CMD_REG );
+ SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
- while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
+ while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
udelay(1); /* Wait until not busy */
/* restore saved registers */
#ifndef CONFIG_XAENIAX
- SMC_outb( saved_pnr, PN_REG );
+ SMC_outb( dev, saved_pnr, PN_REG );
#else
/* On Xaeniax board, we can't use SMC_outb here because that way
* the Allocate MMU command will end up written to the command register
* as well, which will lead to a problem.
*/
- SMC_outl( saved_pnr << 16, 0);
+ SMC_outl( dev, saved_pnr << 16, 0);
#endif
- SMC_outw( saved_ptr, PTR_REG );
+ SMC_outw( dev, saved_ptr, PTR_REG );
if (!is_error) {
/* Pass the packet up to the protocol layers. */
}
-/*----------------------------------------------------
- . smc_close
- .
- . this makes the board clean up everything that it can
- . and not talk to the outside world. Caused by
- . an 'ifconfig ethX down'
- .
- -----------------------------------------------------*/
-static int smc_close()
-{
- PRINTK2("%s: smc_close\n", SMC_DEV_NAME);
-
- /* clear everything */
- smc_shutdown();
-
- return 0;
-}
-
-
#if 0
/*------------------------------------------------------------
. Modify a bit in the LAN91C111 register set
.-------------------------------------------------------------*/
-static word smc_modify_regbit(int bank, int ioaddr, int reg,
+static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
unsigned int bit, int val)
{
word regval;
- SMC_SELECT_BANK( bank );
+ SMC_SELECT_BANK( dev, bank );
- regval = SMC_inw( reg );
+ regval = SMC_inw( dev, reg );
if (val)
regval |= bit;
else
regval &= ~bit;
- SMC_outw( regval, 0 );
+ SMC_outw( dev, regval, 0 );
return(regval);
}
/*------------------------------------------------------------
. Retrieve a bit in the LAN91C111 register set
.-------------------------------------------------------------*/
-static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit)
+static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
{
- SMC_SELECT_BANK( bank );
- if ( SMC_inw( reg ) & bit)
+ SMC_SELECT_BANK( dev, bank );
+ if ( SMC_inw( dev, reg ) & bit)
return(1);
else
return(0);
/*------------------------------------------------------------
. Modify a LAN91C111 register (word access only)
.-------------------------------------------------------------*/
-static void smc_modify_reg(int bank, int ioaddr, int reg, word val)
+static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
{
- SMC_SELECT_BANK( bank );
- SMC_outw( val, reg );
+ SMC_SELECT_BANK( dev, bank );
+ SMC_outw( dev, val, reg );
}
/*------------------------------------------------------------
. Retrieve a LAN91C111 register (word access only)
.-------------------------------------------------------------*/
-static int smc_get_reg(int bank, int ioaddr, int reg)
+static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
{
- SMC_SELECT_BANK( bank );
- return(SMC_inw( reg ));
+ SMC_SELECT_BANK( dev, bank );
+ return(SMC_inw( dev, reg ));
}
#endif /* 0 */
. Reads a register from the MII Management serial interface
.-------------------------------------------------------------*/
#ifndef CONFIG_SMC91111_EXT_PHY
-static word smc_read_phy_register (byte phyreg)
+static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
{
int oldBank;
int i;
bits[clk_idx++] = 0;
/* Save the current bank */
- oldBank = SMC_inw (BANK_SELECT);
+ oldBank = SMC_inw (dev, BANK_SELECT);
/* Select bank 3 */
- SMC_SELECT_BANK (3);
+ SMC_SELECT_BANK (dev, 3);
/* Get the current MII register value */
- mii_reg = SMC_inw (MII_REG);
+ mii_reg = SMC_inw (dev, MII_REG);
/* Turn off all MII Interface bits */
mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
/* Clock all 64 cycles */
for (i = 0; i < sizeof bits; ++i) {
/* Clock Low - output data */
- SMC_outw (mii_reg | bits[i], MII_REG);
+ SMC_outw (dev, mii_reg | bits[i], MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
/* Clock Hi - input data */
- SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
+ SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
- bits[i] |= SMC_inw (MII_REG) & MII_MDI;
+ bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
}
/* Return to idle state */
/* Set clock to low, data to low, and output tristated */
- SMC_outw (mii_reg, MII_REG);
+ SMC_outw (dev, mii_reg, MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
/* Restore original bank select */
- SMC_SELECT_BANK (oldBank);
+ SMC_SELECT_BANK (dev, oldBank);
/* Recover input data */
phydata = 0;
/*------------------------------------------------------------
. Writes a register to the MII Management serial interface
.-------------------------------------------------------------*/
-static void smc_write_phy_register (byte phyreg, word phydata)
+static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
+ word phydata)
{
int oldBank;
int i;
bits[clk_idx++] = 0;
/* Save the current bank */
- oldBank = SMC_inw (BANK_SELECT);
+ oldBank = SMC_inw (dev, BANK_SELECT);
/* Select bank 3 */
- SMC_SELECT_BANK (3);
+ SMC_SELECT_BANK (dev, 3);
/* Get the current MII register value */
- mii_reg = SMC_inw (MII_REG);
+ mii_reg = SMC_inw (dev, MII_REG);
/* Turn off all MII Interface bits */
mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
/* Clock all cycles */
for (i = 0; i < sizeof bits; ++i) {
/* Clock Low - output data */
- SMC_outw (mii_reg | bits[i], MII_REG);
+ SMC_outw (dev, mii_reg | bits[i], MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
/* Clock Hi - input data */
- SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
+ SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
- bits[i] |= SMC_inw (MII_REG) & MII_MDI;
+ bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
}
/* Return to idle state */
/* Set clock to low, data to low, and output tristated */
- SMC_outw (mii_reg, MII_REG);
+ SMC_outw (dev, mii_reg, MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
/* Restore original bank select */
- SMC_SELECT_BANK (oldBank);
+ SMC_SELECT_BANK (dev, oldBank);
#if (SMC_DEBUG > 2 )
printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
. smc_phy_fixed() if the user has requested a certain config.
.-------------------------------------------------------------*/
#ifndef CONFIG_SMC91111_EXT_PHY
-static void smc_phy_configure ()
+static void smc_phy_configure (struct eth_device *dev)
{
int timeout;
byte phyaddr;
phyaddr = SMC_PHY_ADDR;
/* Reset the PHY, setting all other bits to zero */
- smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST);
+ smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
/* Wait for the reset to complete, or time out */
timeout = 6; /* Wait up to 3 seconds */
while (timeout--) {
- if (!(smc_read_phy_register (PHY_CNTL_REG)
+ if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
& PHY_CNTL_RST)) {
/* reset complete */
break;
/* Enable PHY Interrupts (for register 18) */
/* Interrupts listed here are disabled */
- smc_write_phy_register (PHY_MASK_REG, 0xffff);
+ smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
/* Configure the Receive/Phy Control register */
- SMC_SELECT_BANK (0);
- SMC_outw (RPC_DEFAULT, RPC_REG);
+ SMC_SELECT_BANK (dev, 0);
+ SMC_outw (dev, RPC_DEFAULT, RPC_REG);
/* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
- my_phy_caps = smc_read_phy_register (PHY_STAT_REG);
+ my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
if (my_phy_caps & PHY_STAT_CAP_T4)
my_ad_caps |= PHY_AD_10_HDX;
/* Update our Auto-Neg Advertisement Register */
- smc_write_phy_register (PHY_AD_REG, my_ad_caps);
+ smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
/* Read the register back. Without this, it appears that when */
/* auto-negotiation is restarted, sometimes it isn't ready and */
/* the link does not come up. */
- smc_read_phy_register(PHY_AD_REG);
+ smc_read_phy_register(dev, PHY_AD_REG);
PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
/* Restart auto-negotiation process in order to advertise my caps */
- smc_write_phy_register (PHY_CNTL_REG,
+ smc_write_phy_register (dev, PHY_CNTL_REG,
PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
/* Wait for the auto-negotiation to complete. This may take from */
timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
while (timeout--) {
- status = smc_read_phy_register (PHY_STAT_REG);
+ status = smc_read_phy_register (dev, PHY_STAT_REG);
if (status & PHY_STAT_ANEG_ACK) {
/* auto-negotiate complete */
break;
/* Restart auto-negotiation */
printf ("%s: PHY restarting auto-negotiation\n",
SMC_DEV_NAME);
- smc_write_phy_register (PHY_CNTL_REG,
+ smc_write_phy_register (dev, PHY_CNTL_REG,
PHY_CNTL_ANEG_EN |
PHY_CNTL_ANEG_RST |
PHY_CNTL_SPEED |
}
/* Re-Configure the Receive/Phy Control register */
- SMC_outw (RPC_DEFAULT, RPC_REG);
+ SMC_outw (dev, RPC_DEFAULT, RPC_REG);
smc_phy_configure_exit: ;
}
#endif
-int eth_init(bd_t *bd) {
-#ifdef SHARED_RESOURCES
- swap_to(ETHERNET);
-#endif
- return (smc_open(bd));
-}
-
-void eth_halt() {
- smc_close();
-}
-
-int eth_rx() {
- return smc_rcv();
-}
-
-int eth_send(volatile void *packet, int length) {
- return smc_send_packet(packet, length);
-}
-
-int smc_get_ethaddr (bd_t * bd)
+int smc91111_initialize(u8 dev_num, int base_addr)
{
- uchar v_mac[6];
+ struct smc91111_priv *priv;
+ struct eth_device *dev;
+ int i;
- if (!eth_getenv_enetaddr("ethaddr", v_mac)) {
- /* get ROM mac value if any */
- if (!get_rom_mac(v_mac)) {
- printf("\n*** ERROR: ethaddr is NOT set !!\n");
- return -1;
- }
- eth_setenv_enetaddr("ethaddr", v_mac);
+ priv = malloc(sizeof(*priv));
+ if (!priv)
+ return 0;
+ dev = malloc(sizeof(*dev));
+ if (!dev) {
+ free(priv);
+ return 0;
}
- smc_set_mac_addr(v_mac); /* use old function to update smc default */
- PRINTK("Using MAC Address %pM\n", v_mac);
- return 0;
-}
+ priv->dev_num = dev_num;
+ dev->priv = priv;
+ dev->iobase = base_addr;
-int get_rom_mac (uchar *v_rom_mac)
-{
-#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
- char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
-
- memcpy (v_rom_mac, hw_mac_addr, 6);
- return (1);
-#else
- int i;
- int valid_mac = 0;
+ swap_to(ETHERNET);
+ SMC_SELECT_BANK(dev, 1);
+ for (i = 0; i < 6; ++i)
+ dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
+ swap_to(FLASH);
- SMC_SELECT_BANK (1);
- for (i=0; i<6; i++)
- {
- v_rom_mac[i] = SMC_inb ((ADDR0_REG + i));
- valid_mac |= v_rom_mac[i];
- }
+ dev->init = smc_init;
+ dev->halt = smc_halt;
+ dev->send = smc_send;
+ dev->recv = smc_rcv;
+ sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
- return (valid_mac ? 1 : 0);
-#endif
+ eth_register(dev);
+ return 0;
}
typedef unsigned short word;
typedef unsigned long int dword;
+struct smc91111_priv{
+ u8 dev_num;
+};
+
/*
. DEBUGGING LEVELS
.
#ifdef CONFIG_PXA250
#ifdef CONFIG_XSENGINE
-#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
-#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))))
-#define SMC_inb(p) ({ \
- unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \
+#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1))))
+#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r<<1))))
+#define SMC_inb(a,p) ({ \
+ unsigned int __p = (unsigned int)((a)->iobase + (p<<1)); \
unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
if (__p & 2) __v >>= 8; \
else __v &= 0xff; \
__v; })
#elif defined(CONFIG_XAENIAX)
-#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
-#define SMC_inw(z) ({ \
- unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (z)); \
+#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
+#define SMC_inw(a,z) ({ \
+ unsigned int __p = (unsigned int)((a)->iobase + (z)); \
unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \
if (__p & 3) __v >>= 16; \
else __v &= 0xffff; \
__v; })
-#define SMC_inb(p) ({ \
- unsigned int ___v = SMC_inw((p) & ~1); \
+#define SMC_inb(a,p) ({ \
+ unsigned int ___v = SMC_inw((a),(p) & ~1); \
if (p & 1) ___v >>= 8; \
else ___v &= 0xff; \
___v; })
#else
-#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
-#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
-#define SMC_inb(p) ({ \
- unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \
+#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
+#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r))))
+#define SMC_inb(a,p) ({ \
+ unsigned int __p = (unsigned int)((a)->iobase + (p)); \
unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
if (__p & 1) __v >>= 8; \
else __v &= 0xff; \
#endif
#ifdef CONFIG_XSENGINE
-#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d)
-#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))) = d)
+#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d)
+#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d)
#elif defined (CONFIG_XAENIAX)
-#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
-#define SMC_outw(d,p) ({ \
- dword __dwo = SMC_inl((p) & ~3); \
+#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
+#define SMC_outw(a,d,p) ({ \
+ dword __dwo = SMC_inl((a),(p) & ~3); \
dword __dwn = (word)(d); \
__dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \
__dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \
- SMC_outl(__dwo, (p) & ~3); \
+ SMC_outl((a), __dwo, (p) & ~3); \
})
#else
-#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
-#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
+#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
+#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d)
#endif
-#define SMC_outb(d,r) ({ word __d = (byte)(d); \
- word __w = SMC_inw((r)&~1); \
+#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \
+ word __w = SMC_inw((a),(r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
__w |= ((r)&1) ? __d<<8 : __d; \
- SMC_outw(__w,(r)&~1); \
+ SMC_outw((a),__w,(r)&~1); \
})
-#define SMC_outsl(r,b,l) ({ int __i; \
+#define SMC_outsl(a,r,b,l) ({ int __i; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outl( *(__b2 + __i), r); \
+ SMC_outl((a), *(__b2 + __i), r); \
} \
})
-#define SMC_outsw(r,b,l) ({ int __i; \
+#define SMC_outsw(a,r,b,l) ({ int __i; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outw( *(__b2 + __i), r); \
+ SMC_outw((a), *(__b2 + __i), r); \
} \
})
-#define SMC_insl(r,b,l) ({ int __i ; \
+#define SMC_insl(a,r,b,l) ({ int __i ; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inl(r); \
- SMC_inl(0); \
+ *(__b2 + __i) = SMC_inl((a),(r)); \
+ SMC_inl((a),0); \
}; \
})
-#define SMC_insw(r,b,l) ({ int __i ; \
+#define SMC_insw(a,r,b,l) ({ int __i ; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inw(r); \
- SMC_inw(0); \
+ *(__b2 + __i) = SMC_inw((a),(r)); \
+ SMC_inw((a),0); \
}; \
})
-#define SMC_insb(r,b,l) ({ int __i ; \
+#define SMC_insb(a,r,b,l) ({ int __i ; \
byte *__b2; \
__b2 = (byte *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inb(r); \
- SMC_inb(0); \
+ *(__b2 + __i) = SMC_inb((a),(r)); \
+ SMC_inb((a),0); \
}; \
})
((0x00FF0000UL & _x) >> 8) | \
(_x >> 24)); })
-#define SMC_inl(r) (SMC_LEON_SWAP32((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0)))))
-#define SMC_inl_nosw(r) ((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))))
-#define SMC_inw(r) (SMC_LEON_SWAP16((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0)))))
-#define SMC_inw_nosw(r) ((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))))
-#define SMC_inb(p) ({ \
- word ___v = SMC_inw((p) & ~1); \
+#define SMC_inl(a,r) (SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0)))))
+#define SMC_inl_nosw(a,r) ((*(volatile dword *)((a)->iobase+((r)<<0))))
+#define SMC_inw(a,r) (SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0)))))
+#define SMC_inw_nosw(a,r) ((*(volatile word *)((a)->iobase+((r)<<0))))
+#define SMC_inb(a,p) ({ \
+ word ___v = SMC_inw((a),(p) & ~1); \
if ((p) & 1) ___v >>= 8; \
else ___v &= 0xff; \
___v; })
-#define SMC_outl(d,r) (*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))=SMC_LEON_SWAP32(d))
-#define SMC_outl_nosw(d,r) (*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))=(d))
-#define SMC_outw(d,r) (*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))=SMC_LEON_SWAP16(d))
-#define SMC_outw_nosw(d,r) (*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))=(d))
-#define SMC_outb(d,r) do{ word __d = (byte)(d); \
- word __w = SMC_inw((r)&~1); \
+#define SMC_outl(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d))
+#define SMC_outl_nosw(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=(d))
+#define SMC_outw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d))
+#define SMC_outw_nosw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=(d))
+#define SMC_outb(a,d,r) do{ word __d = (byte)(d); \
+ word __w = SMC_inw((a),(r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
__w |= ((r)&1) ? __d<<8 : __d; \
- SMC_outw(__w,(r)&~1); \
+ SMC_outw((a),__w,(r)&~1); \
}while(0)
-#define SMC_outsl(r,b,l) do{ int __i; \
+#define SMC_outsl(a,r,b,l) do{ int __i; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outl_nosw( *(__b2 + __i), r); \
+ SMC_outl_nosw((a), *(__b2 + __i), r); \
} \
}while(0)
-#define SMC_outsw(r,b,l) do{ int __i; \
+#define SMC_outsw(a,r,b,l) do{ int __i; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outw_nosw( *(__b2 + __i), r); \
+ SMC_outw_nosw((a), *(__b2 + __i), r); \
} \
}while(0)
-#define SMC_insl(r,b,l) do{ int __i ; \
+#define SMC_insl(a,r,b,l) do{ int __i ; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inl_nosw(r); \
+ *(__b2 + __i) = SMC_inl_nosw((a),(r)); \
}; \
}while(0)
-#define SMC_insw(r,b,l) do{ int __i ; \
+#define SMC_insw(a,r,b,l) do{ int __i ; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inw_nosw(r); \
+ *(__b2 + __i) = SMC_inw_nosw((a),(r)); \
}; \
}while(0)
-#define SMC_insb(r,b,l) do{ int __i ; \
+#define SMC_insb(a,r,b,l) do{ int __i ; \
byte *__b2; \
__b2 = (byte *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inb(r); \
+ *(__b2 + __i) = SMC_inb((a),(r)); \
}; \
}while(0)
*/
#ifdef CONFIG_ADNPESC1
-#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))))
+#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
#elif CONFIG_BLACKFIN
-#define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); SSYNC(); __v;})
+#define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;})
#else
-#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))))
+#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r))))
#endif
-#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)
+#define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))
#ifdef CONFIG_ADNPESC1
-#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d)
+#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d)
#elif CONFIG_BLACKFIN
-#define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d); SSYNC();}
+#define SMC_outw(a,d,r) {(*((volatile word *)((a)->iobase+(r))) = d); SSYNC();}
#else
-#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
+#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d)
#endif
-#define SMC_outb(d,r) ({ word __d = (byte)(d); \
- word __w = SMC_inw((r)&~1); \
+#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \
+ word __w = SMC_inw((a),(r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
__w |= ((r)&1) ? __d<<8 : __d; \
- SMC_outw(__w,(r)&~1); \
+ SMC_outw((a),__w,(r)&~1); \
})
#if 0
-#define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l))
+#define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l))
#else
-#define SMC_outsw(r,b,l) ({ int __i; \
+#define SMC_outsw(a,r,b,l) ({ int __i; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outw( *(__b2 + __i), r); \
+ SMC_outw((a), *(__b2 + __i), r); \
} \
})
#endif
#if 0
-#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l))
+#define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l))
#else
-#define SMC_insw(r,b,l) ({ int __i ; \
+#define SMC_insw(a,r,b,l) ({ int __i ; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inw(r); \
- SMC_inw(0); \
+ *(__b2 + __i) = SMC_inw((a),(r)); \
+ SMC_inw((a),0); \
}; \
})
#endif
#if defined(CONFIG_SMC_USE_32_BIT)
#ifdef CONFIG_XSENGINE
-#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))))
+#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1))))
#else
-#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
+#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
#endif
-#define SMC_insl(r,b,l) ({ int __i ; \
+#define SMC_insl(a,r,b,l) ({ int __i ; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
- *(__b2 + __i) = SMC_inl(r); \
- SMC_inl(0); \
+ *(__b2 + __i) = SMC_inl((a),(r)); \
+ SMC_inl((a),0); \
}; \
})
#ifdef CONFIG_XSENGINE
-#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d)
+#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d)
#else
-#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d)
+#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
#endif
-#define SMC_outsl(r,b,l) ({ int __i; \
+#define SMC_outsl(a,r,b,l) ({ int __i; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
- SMC_outl( *(__b2 + __i), r); \
+ SMC_outl((a), *(__b2 + __i), r); \
} \
})
/* select a register bank, 0 to 3 */
-#define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); }
+#define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); }
/* this enables an interrupt in the interrupt mask register */
-#define SMC_ENABLE_INT(x) {\
+#define SMC_ENABLE_INT(a,x) {\
unsigned char mask;\
- SMC_SELECT_BANK(2);\
- mask = SMC_inb( IM_REG );\
+ SMC_SELECT_BANK((a),2);\
+ mask = SMC_inb((a), IM_REG );\
mask |= (x);\
- SMC_outb( mask, IM_REG ); \
+ SMC_outb( (a), mask, IM_REG ); \
}
/* this disables an interrupt from the interrupt mask register */
-#define SMC_DISABLE_INT(x) {\
+#define SMC_DISABLE_INT(a,x) {\
unsigned char mask;\
SMC_SELECT_BANK(2);\
- mask = SMC_inb( IM_REG );\
+ mask = SMC_inb( (a), IM_REG );\
mask &= ~(x);\
- SMC_outb( mask, IM_REG ); \
+ SMC_outb( (a), mask, IM_REG ); \
}
/*----------------------------------------------------------------------
#include <common.h>
#include <exports.h>
+/* the smc91111.h gets base addr through eth_device' iobase */
+struct eth_device { unsigned long iobase; };
#include "../drivers/net/smc91111.h"
-#ifdef CONFIG_DRIVER_SMC91111
+#ifdef CONFIG_SMC91111
#ifndef SMC91111_EEPROM_INIT
# define SMC91111_EEPROM_INIT()
#define MAC 0x2
#define UNKNOWN 0x4
-void dump_reg (void);
-void dump_eeprom (void);
-int write_eeprom_reg (int, int);
-void copy_from_eeprom (void);
-void print_MAC (void);
-int read_eeprom_reg (int);
-void print_macaddr (void);
+void dump_reg (struct eth_device *dev);
+void dump_eeprom (struct eth_device *dev);
+int write_eeprom_reg (struct eth_device *dev, int value, int reg);
+void copy_from_eeprom (struct eth_device *dev);
+void print_MAC (struct eth_device *dev);
+int read_eeprom_reg (struct eth_device *dev, int reg);
+void print_macaddr (struct eth_device *dev);
int smc91111_eeprom (int argc, char *argv[])
{
int c, i, j, done, line, reg, value, start, what;
char input[50];
+ struct eth_device dev = {
+ .iobase = CONFIG_SMC91111_BASE
+ };
+
/* Print the ABI version */
app_startup (argv);
if (XF_VERSION != (int) get_version ()) {
SMC91111_EEPROM_INIT();
- if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
+ if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
printf ("Can't find SMSC91111\n");
return (0);
}
switch (what) {
case 1:
printf ("Writing EEPROM register %02x with %04x\n", reg, value);
- write_eeprom_reg (value, reg);
+ write_eeprom_reg (&dev, value, reg);
break;
case 2:
printf ("Writing MAC register bank %i, reg %02x with %04x\n", reg >> 4, reg & 0xE, value);
- SMC_SELECT_BANK (reg >> 4);
- SMC_outw (value, reg & 0xE);
+ SMC_SELECT_BANK (&dev, reg >> 4);
+ SMC_outw (&dev, value, reg & 0xE);
break;
default:
printf ("Wrong\n");
}
break;
case ('D'):
- dump_eeprom ();
+ dump_eeprom (&dev);
break;
case ('M'):
- dump_reg ();
+ dump_reg (&dev);
break;
case ('C'):
- copy_from_eeprom ();
+ copy_from_eeprom (&dev);
break;
case ('P'):
- print_macaddr ();
+ print_macaddr (&dev);
break;
default:
break;
return (0);
}
-void copy_from_eeprom (void)
+void copy_from_eeprom (struct eth_device *dev)
{
int i;
- SMC_SELECT_BANK (1);
- SMC_outw ((SMC_inw (CTL_REG) & !CTL_EEPROM_SELECT) | CTL_RELOAD,
- CTL_REG);
+ SMC_SELECT_BANK (dev, 1);
+ SMC_outw (dev, (SMC_inw (dev, CTL_REG) & !CTL_EEPROM_SELECT) |
+ CTL_RELOAD, CTL_REG);
i = 100;
- while ((SMC_inw (CTL_REG) & CTL_RELOAD) && --i)
+ while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --i)
udelay (100);
if (i == 0) {
printf ("Timeout Refreshing EEPROM registers\n");
}
-void print_macaddr (void)
+void print_macaddr (struct eth_device *dev)
{
int i, j, k, mac[6];
printf ("Current MAC Address in SMSC91111 ");
- SMC_SELECT_BANK (1);
+ SMC_SELECT_BANK (dev, 1);
for (i = 0; i < 5; i++) {
- printf ("%02x:", SMC_inb (ADDR0_REG + i));
+ printf ("%02x:", SMC_inb (dev, ADDR0_REG + i));
}
- printf ("%02x\n", SMC_inb (ADDR0_REG + 5));
+ printf ("%02x\n", SMC_inb (dev, ADDR0_REG + 5));
i = 0;
for (j = 0x20; j < 0x23; j++) {
- k = read_eeprom_reg (j);
+ k = read_eeprom_reg (dev, j);
mac[i] = k & 0xFF;
i++;
mac[i] = k >> 8;
printf ("%02x\n", mac[5]);
}
-void dump_eeprom (void)
+void dump_eeprom (struct eth_device *dev)
{
int j, k;
if ((k == 2) || (k == 3))
printf (" ");
for (j = 0; j < 0x20; j += 4) {
- printf ("%02x:%04x ", j + k, read_eeprom_reg (j + k));
+ printf ("%02x:%04x ", j + k,
+ read_eeprom_reg (dev, j + k));
}
printf ("\n");
}
for (j = 0x20; j < 0x40; j++) {
if ((j & 0x07) == 0)
printf ("\n");
- printf ("%02x:%04x ", j, read_eeprom_reg (j));
+ printf ("%02x:%04x ", j, read_eeprom_reg (dev, j));
}
printf ("\n");
}
-int read_eeprom_reg (int reg)
+int read_eeprom_reg (struct eth_device *dev, int reg)
{
int timeout;
- SMC_SELECT_BANK (2);
- SMC_outw (reg, PTR_REG);
+ SMC_SELECT_BANK (dev, 2);
+ SMC_outw (dev, reg, PTR_REG);
- SMC_SELECT_BANK (1);
- SMC_outw (SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
- CTL_REG);
+ SMC_SELECT_BANK (dev, 1);
+ SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT |
+ CTL_RELOAD, CTL_REG);
timeout = 100;
- while ((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout)
+ while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
udelay (100);
if (timeout == 0) {
printf ("Timeout Reading EEPROM register %02x\n", reg);
return 0;
}
- return SMC_inw (GP_REG);
+ return SMC_inw (dev, GP_REG);
}
-int write_eeprom_reg (int value, int reg)
+int write_eeprom_reg (struct eth_device *dev, int value, int reg)
{
int timeout;
- SMC_SELECT_BANK (2);
- SMC_outw (reg, PTR_REG);
+ SMC_SELECT_BANK (dev, 2);
+ SMC_outw (dev, reg, PTR_REG);
- SMC_SELECT_BANK (1);
- SMC_outw (value, GP_REG);
- SMC_outw (SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
+ SMC_SELECT_BANK (dev, 1);
+ SMC_outw (dev, value, GP_REG);
+ SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT |
+ CTL_STORE, CTL_REG);
timeout = 100;
- while ((SMC_inw (CTL_REG) & CTL_STORE) && --timeout)
+ while ((SMC_inw (dev, CTL_REG) & CTL_STORE) && --timeout)
udelay (100);
if (timeout == 0) {
printf ("Timeout Writing EEPROM register %02x\n", reg);
}
-void dump_reg (void)
+void dump_reg (struct eth_device *dev)
{
int i, j;
for (i = 0; i < 0xF; i += 2) {
printf ("%02x ", i);
for (j = 0; j < 4; j++) {
- SMC_SELECT_BANK (j);
- printf ("%04x ", SMC_inw (i));
+ SMC_SELECT_BANK (dev, j);
+ printf ("%04x ", SMC_inw (dev, i));
}
printf ("\n");
}
* cache bypass so there's no need to monkey with inx/outx macros.
*----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
-#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
* cache bypass so there's no need to monkey with inx/outx macros.
*----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
-#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
* cache bypass so there's no need to monkey with inx/outx macros.
*----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
-#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9111 */
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0xB0000000)
/* MEMORY */
* cache bypass so there's no need to monkey with inx/outx macros.
*----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
-#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20310300
#define SMC91111_EEPROM_INIT() \
do { \
- *pFIO_DIR |= PF1; \
- *pFIO_FLAG_S = PF1; \
+ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
+ bfin_write_FIO_FLAG_C(PF1); \
+ bfin_write_FIO_FLAG_S(PF0); \
SSYNC(); \
} while (0)
#define CONFIG_HOSTNAME bf533-ezkit
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20300300
#define SMC91111_EEPROM_INIT() \
do { \
- *pFIO_DIR |= PF1; \
- *pFIO_FLAG_S = PF1; \
+ bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
+ bfin_write_FIO_FLAG_C(PF1); \
+ bfin_write_FIO_FLAG_S(PF0); \
SSYNC(); \
} while (0)
#define CONFIG_HOSTNAME bf533-stamp
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20310300
#define CONFIG_HOSTNAME bf538f-ezkit
/* Uncomment next line to use fixed MAC address */
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x2C010300
#define CONFIG_SMC_USE_32_BIT 1
#define CONFIG_HOSTNAME bf561-ezkit
/*
* Board settings
*/
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20300300
/* FLASH/ETHERNET uses the same address range
* Network settings
*/
-#ifdef CONFIG_DRIVER_SMC91111
+#ifdef CONFIG_SMC91111
#define CONFIG_IPADDR 192.168.0.15
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_GATEWAYIP 192.168.0.1
#include <config_cmd_default.h>
-#ifdef CONFIG_DRIVER_SMC91111
+#ifdef CONFIG_SMC91111
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_PING
#else
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE 0x04000300
#define CONFIG_SMC_USE_32_BIT
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20200300
#define CONFIG_HOSTNAME cm-bf533
/* Uncomment next line to use fixed MAC address */
*/
#define ADI_CMDS_NETWORK 1
/* The next 2 lines are for use with DEV-BF5xx */
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x28000300
/* The next 3 lines are for use with EXT-BF5xx-USB-ETH2 */
/* #define CONFIG_DRIVER_SMC911X 1 */
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE 0x10000300
#define CONFIG_SMC91111_EXT_PHY
#define CONFIG_SMC_USE_32_BIT
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE 0x20000300
/*
* Ethernet configuration uses on board SMC91C111
*/
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
#ifndef USE_GRETH
/* USE SMC91C111 MAC */
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
/*
* SMSC91C111 Network Card
*/
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */
#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC_USE_32_BIT
#define CONFIG_SMC91111_BASE 0xC8000000
#undef CONFIG_SMC91111_EXT_PHY
* SMSC91C111 Network Card
*/
#if 0
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x10000000 /* chip select 4 */
#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
* Default IO base of chip is 0x300, Card Engine has this address lines
* (LAN chip) tied to Vcc, so we just care about the chip select
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0x70000000)
#undef CONFIG_SMC_USE_32_BIT
#define CONFIG_SMC_USE_IOFUNCS
* Default IO base of chip is 0x300, Card Engine has this address lines
* (LAN chip) tied to Vcc, so we just care about the chip select
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0x70000000)
#undef CONFIG_SMC_USE_32_BIT
#define CONFIG_SMC_USE_IOFUNCS
#undef CONFIG_SHOW_BOOT_PROGRESS
/* SMC9111 */
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (0xB8000000)
/* MEMORY */
#define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */
#define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE 0x04000300
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR)
-#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111*/
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 /* Using SMC91c111*/
#define CONFIG_SMC91111_BASE 0x34000300
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
#define CONFIG_SMC_USE_32_BIT 1
/* #define CONFIG_SMC_USE_IOFUNCS */
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC_USE_32_BIT
#define CONFIG_SMC91111_BASE 0x10010000
#undef CONFIG_SMC91111_EXT_PHY
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE 0x08000300
#define CONFIG_HARD_I2C
/*
* SMSC91C111 Network Card
*/
-#define CONFIG_DRIVER_SMC91111 1
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */
#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
/*
* Hardware drivers
*/
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE 0x04000300
#undef CONFIG_SMC91111_EXT_PHY
#define CONFIG_SMC_USE_32_BIT
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/* Hardware drivers */
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
#define CONFIG_SMC91111_BASE 0x04000300
#define CONFIG_SMC_USE_32_BIT 1
#undef TURN_ON_ETHERNET
#ifdef TURN_ON_ETHERNET
-# define CONFIG_DRIVER_SMC91111 1
+# define CONFIG_SMC91111 1
# define CONFIG_SMC91111_BASE 0x14000300
# define CONFIG_SMC91111_EXT_PHY
# define CONFIG_SMC_USE_32_BIT
int scc_initialize(bd_t *bis);
int skge_initialize(bd_t *bis);
int smc911x_initialize(u8 dev_num, int base_addr);
+int smc91111_initialize(u8 dev_num, int base_addr);
int tsi108_eth_initialize(bd_t *bis);
int uec_initialize(int index);
int uec_standard_init(bd_t *bis);
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