ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)

Add config option for 180 degree advance clock control as needed
for the AMCC Luan eval board.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 2ecd3e4b61011cc553675580d99ab530e879fa56..48b9ee2f7e0bacb516ae671f0ae050bf2d80c6e8 100644 (file)
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -465,7 +465,11 @@ long int initdram(int board_type)
         * Set the SDRAM Clock Timing Register
         *-----------------------------------------------------------------*/
        mfsdram(SDRAM_CLKTR, val);
+#ifdef CFG_44x_DDR2_CKTR_180
+       mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_180_DEG_ADV);
+#else
        mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
+#endif
 
        /*------------------------------------------------------------------
         * Program the BxCF registers.
@@ -1117,7 +1121,8 @@ static void program_codt(unsigned long *dimm_populated,
                                modt3 = 0x00000000;
                        }
                        if (total_rank == 4) {
-                               codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | CALC_ODT_R(2) | CALC_ODT_R(3);
+                               codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
+                                       CALC_ODT_R(2) | CALC_ODT_R(3);
                                modt0 = CALC_ODT_RW(2);
                                modt1 = 0x00000000;
                                modt2 = CALC_ODT_RW(0);