Fix two SDRAM setup bugs.

    Fix ECC setup bug.
    Enable 1T/2T based on number of DIMMs present.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>

diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index 130c8fc3961b473b308472268e02059846c01ccf..f30bbbd7e2b53e39b29935a34520a5166ee50cc1 100644 (file)
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -1088,24 +1088,24 @@ unsigned int enable_ddr(unsigned int ddr_num)
                 * If the user wanted ECC (enabled via sdram_cfg[2])
                 */
                if (config == 0x02) {
+                       ddr->err_disable = 0x00000000;
+                       asm("sync;isync;");
+                       ddr->err_sbe = 0x00ff0000;
+                       ddr->err_int_en = 0x0000000d;
                        sdram_cfg_1 |= 0x20000000;              /* ECC_EN */
                }
 #endif
 
                /*
-                * REV1 uses 1T timing.
-                * REV2 may use 1T or 2T as configured by the user.
+                * Set 1T or 2T timing based on 1 or 2 modules
                 */
                {
-                       uint pvr = get_pvr();
-
-                       if (pvr != PVR_85xx_REV1) {
-#if defined(CONFIG_DDR_2T_TIMING)
+                       if (!(no_dimm1 || no_dimm2)) {
                                /*
+                                * 2T timing,because both DIMMS are present.
                                 * Enable 2T timing by setting sdram_cfg[16].
                                 */
                                sdram_cfg_1 |= 0x8000;          /* 2T_EN */
-#endif
                        }
                }