arm: dts: imx8mm-venice-gw7903: add dig1_ctl and dig2_ctl gpios

The GW7903 revision B adds two additional GPIO's to control the
direction of the 2 isolated digital I/O circuits.

Define them as:
 - dig1_ctl
 - dig2_ctl

Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi
index 896e5d4edde35e5ed9d79029913ce501692610fc..ff9b12a83408ed326d7996769b7f031486f554de 100644 (file)
--- a/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi
@@ -43,6 +43,20 @@
                line-name = "dig2_out#";
        };
 
+       dig2ctl {
+               gpio-hog;
+               output-low;
+               gpios = <2 GPIO_ACTIVE_HIGH>;
+               line-name = "dig2_ctl";
+       };
+
+       dig1ctl {
+               gpio-hog;
+               output-low;
+               gpios = <6 GPIO_ACTIVE_HIGH>;
+               line-name = "dig1_ctl";
+       };
+
        dig1out {
                gpio-hog;
                output-high;

diff --git a/arch/arm/dts/imx8mm-venice-gw7903.dts b/arch/arm/dts/imx8mm-venice-gw7903.dts
index a7dae9bd4c118e1d28b71c63d97f393254a0a9dd..1b69ac0e12b073ceee2c6cd0fcea51ef9e90fbd5 100644 (file)
--- a/arch/arm/dts/imx8mm-venice-gw7903.dts
+++ b/arch/arm/dts/imx8mm-venice-gw7903.dts
@@ -250,7 +250,7 @@
 };
 
 &gpio2 {
-       gpio-line-names = "dig2_in", "dig2_out#", "", "", "", "", "", "",
+       gpio-line-names = "dig2_in", "dig2_out#", "dig2_ctl", "", "", "", "dig1_ctl", "",
                "dig1_out#", "dig1_in", "", "", "", "", "", "",
                "", "", "", "", "", "", "", "",
                "", "", "", "", "", "", "", "";
@@ -630,6 +630,8 @@
                        MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x40000041 /* RS232# */
                        MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9        0x40000041 /* DIG1_IN */
                        MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8        0x40000041 /* DIG1_OUT */
+                       MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6        0x40000041 /* DIG1_CTL */
+                       MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2        0x40000041 /* DIG2_CTL */
                        MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0          0x40000041 /* DIG2_IN */
                        MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1          0x40000041 /* DIG2_OUT */
                        MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7      0x40000041 /* SIM1DET# */