ppc4xx: Maintenance patch for esd's CPCI405 derivats

-add pci_pre_init() for pci interrupt fixup code
-disable phy sleep mode via reset_phy() function
-use correct io accessors
-cleanup

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index f80361081a6c080d6011a5fa168724515f8fea3e..263b75d3a1a2162a1d11b3f377a9dfd8589fac97 100644 (file)
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -23,9 +23,11 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <command.h>
 #include <malloc.h>
 #include <net.h>
+#include <pci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -179,11 +181,15 @@ int board_early_init_f (void)
        mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
        mtdcr(uicer, 0x00000000);       /* disable all ints */
        mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+#ifdef CONFIG_CPCI405_6U
        if (cpci405_version() == 3) {
                mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
        } else {
                mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
        }
+#else
+       mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+#endif
        mtdcr(uictr, 0x10000000);       /* set int trigger levels */
        mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
        mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
@@ -227,10 +233,10 @@ int cpci405_version(void)
         */
        cntrl0Reg = mfdcr(cntrl0);
        mtdcr(cntrl0, cntrl0Reg | 0x03000000);
-       out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
-       out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
+       out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
+       out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
        udelay(1000);                   /* wait some time before reading input */
-       value = in32(GPIO0_IR) & 0x00180000;       /* get config bits */
+       value = in_be32((void*)GPIO0_IR) & 0x00180000;       /* get config bits */
 
        /*
         * Restore GPIO settings
@@ -245,7 +251,7 @@ int cpci405_version(void)
                /* CS2==0 && CS3==1 -> version 2 */
                return 2;
        case 0x00100000:
-               /* CS2==1 && CS3==0 -> version 3 */
+               /* CS2==1 && CS3==0 -> version 3 or 6U board */
                return 3;
        case 0x00000000:
                /* CS2==0 && CS3==0 -> version 4 */
@@ -283,7 +289,6 @@ int misc_init_r (void)
         * On CPCI-405 version 2 the environment is saved in eeprom!
         * FPGA can be gzip compressed (malloc) and booted this late.
         */
-
        if (cpci405_version() >= 2) {
                /*
                 * Setup GPIO pins (CS6+CS7 as GPIO)
@@ -354,6 +359,7 @@ int misc_init_r (void)
                SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
                udelay(1000); /* wait 1ms */
 
+#ifdef CONFIG_CPCI405_6U
                if (cpci405_version() == 3) {
                        volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
                        volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
@@ -375,6 +381,7 @@ int misc_init_r (void)
                        udelay(100);
                        *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
                }
+#endif
        }
        else {
                puts("\n*** U-Boot Version does not match Board Version!\n");
@@ -493,12 +500,6 @@ int checkboard (void)
 #endif
 
        putc ('\n');
-
-       /*
-        * Disable sleep mode in LXT971
-        */
-       lxt971_no_sleep();
-
        return 0;
 }
 
@@ -511,24 +512,22 @@ long int initdram (int board_type)
        mtdcr(memcfga, mem_mb0cf);
        val = mfdcr(memcfgd);
 
-#if 0
-       printf("\nmb0cf=%x\n", val); /* test-only */
-       printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
        return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
 
-/* ------------------------------------------------------------------------- */
 
-int testdram (void)
+void reset_phy(void)
 {
-       /* TODO: XXX XXX XXX */
-       printf ("test: 16 MB - ok\n");
+#ifdef CONFIG_LXT971_NO_SLEEP
 
-       return (0);
+       /*
+        * Disable sleep mode in LXT971
+        */
+       lxt971_no_sleep();
+#endif
 }
 
+
 /* ------------------------------------------------------------------------- */
 
 #ifdef CONFIG_CPCI405_VER2
@@ -552,6 +551,41 @@ void ide_set_reset(int on)
 #endif /* CONFIG_CPCI405_VER2 */
 
 
+#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
+void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+       unsigned char int_line = 0xff;
+
+       /*
+        * Write pci interrupt line register (cpci405 specific)
+        */
+       switch (PCI_DEV(dev) & 0x03) {
+       case 0:
+               int_line = 27 + 2;
+               break;
+       case 1:
+               int_line = 27 + 3;
+               break;
+       case 2:
+               int_line = 27 + 0;
+               break;
+       case 3:
+               int_line = 27 + 1;
+               break;
+       }
+
+       pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
+}
+
+int pci_pre_init(struct pci_controller *hose)
+{
+       hose->fixup_irq = cpci405_pci_fixup_irq;
+       return 1;
+}
+#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
+
+
+
 #ifdef CONFIG_CPCI405AB
 
 #define ONE_WIRE_CLEAR   (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \

diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index 047e2f1eef9cc57f7a5ba6517de8cf828d2f358b..67f7581130152596a9ace3885088d80bb2d5089b 100644 (file)
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -55,6 +55,10 @@
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                0       /* PHY address                  */
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI       1
+#undef  CONFIG_HAS_ETH1
 
 #define CONFIG_BOOTP_MASK      (CONFIG_BOOTP_DEFAULT | \
                                 CONFIG_BOOTP_DNS | \
@@ -139,6 +143,7 @@
 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 
 #define CONFIG_PCI                     /* include pci support          */
+#define CFG_PCI_PRE_INIT                /* pci interrupt mapping etc.   */
 #define CONFIG_PCI_HOST        PCI_HOST_AUTO   /* select pci host function     */
 #define CONFIG_PCI_PNP                 /* do pci plug-and-play         */
                                        /* resource configuration       */

diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index d756f447f7faed06880c80c343de219f93b836de..8abdbdc6df2eadc9ae920167c06feee95d304e6e 100644 (file)
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -37,6 +37,7 @@
 #define CONFIG_4xx             1       /* ...member of PPC4xx family   */
 #define CONFIG_CPCI405         1       /* ...on a CPCI405 board        */
 #define CONFIG_CPCI405_VER2    1       /* ...version 2                 */
+#undef  CONFIG_CPCI405_6U               /* enable this for 6U boards    */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1    /* call board_early_init_f()    */
 
@@ -56,6 +57,10 @@
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                0       /* PHY address                  */
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI       1
+#undef  CONFIG_HAS_ETH1
 
 #define CONFIG_RTC_M48T35A     1               /* ST Electronics M48 timekeeper */
 
@@ -166,6 +171,7 @@
 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 
 #define CONFIG_PCI                     /* include pci support          */
+#define CFG_PCI_PRE_INIT                /* pci interrupt mapping etc.   */
 #define CONFIG_PCI_HOST        PCI_HOST_AUTO   /* select pci host function     */
 #define CONFIG_PCI_PNP                 /* do pci plug-and-play         */
                                        /* resource configuration       */

diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 852d94a410ac8a45de3b0a8daaf110fa0de9559d..ab6d1168f1de310e6bbb53a1b9cad7ce406daef3 100644 (file)
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -57,6 +57,10 @@
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                0       /* PHY address                  */
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI       1
+#undef  CONFIG_HAS_ETH1
 
 #define CONFIG_RTC_M48T35A     1               /* ST Electronics M48 timekeeper */
 
@@ -150,6 +154,7 @@
 #define PCI_HOST_AUTO  2               /* detected via arbiter enable  */
 
 #define CONFIG_PCI                     /* include pci support          */
+#define CFG_PCI_PRE_INIT                /* pci interrupt mapping etc.   */
 #define CONFIG_PCI_HOST PCI_HOST_AUTO  /* select pci host function     */
 #define CONFIG_PCI_PNP                 /* do pci plug-and-play         */
                                        /* resource configuration       */

diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index 2260327c3f855ba88a3429695bae0b7c875abe20..42ec0801ad79edffc51d5d4b37b7ce309645f130 100644 (file)
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -56,6 +56,10 @@
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                0       /* PHY address                  */
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI       1
+#undef  CONFIG_HAS_ETH1
 
 #define CONFIG_RTC_M48T35A     1               /* ST Electronics M48 timekeeper */
 
@@ -171,6 +175,7 @@
 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 
 #define CONFIG_PCI                     /* include pci support          */
+#define CFG_PCI_PRE_INIT                /* pci interrupt mapping etc.   */
 #define CONFIG_PCI_HOST        PCI_HOST_AUTO   /* select pci host function     */
 #define CONFIG_PCI_PNP                 /* do pci plug-and-play         */
                                        /* resource configuration       */