]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
fsl-layerscape: Add RESV_RAM check in resv_ram addr
authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Tue, 28 Apr 2020 02:19:28 +0000 (10:19 +0800)
committerPriyanka Jain <priyanka.jain@nxp.com>
Tue, 28 Apr 2020 12:16:46 +0000 (17:46 +0530)
The initialization of gd->arch.resv_ram pointer should depend on if the
RESV_RAM config is enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/cpu.c

index b44389445369c852a6be3b2bcd63c29956221fad..1b7729c046751cbd014d5ed46125ae6e7119ca7f 100644 (file)
@@ -1379,7 +1379,7 @@ static int tfa_dram_init_banksize(void)
        if (i > 0)
                ret = 0;
 
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
        /* Assign memory for MC */
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
        if (gd->bd->bi_dram[2].size >=
@@ -1402,7 +1402,7 @@ static int tfa_dram_init_banksize(void)
                                board_reserve_ram_top(gd->bd->bi_dram[0].size);
                }
        }
-#endif /* CONFIG_FSL_MC_ENET */
+#endif /* CONFIG_RESV_RAM */
 
        return ret;
 }
@@ -1465,7 +1465,7 @@ int dram_init_banksize(void)
        }
 #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
 
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
        /* Assign memory for MC */
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
        if (gd->bd->bi_dram[2].size >=
@@ -1488,7 +1488,7 @@ int dram_init_banksize(void)
                                board_reserve_ram_top(gd->bd->bi_dram[0].size);
                }
        }
-#endif /* CONFIG_FSL_MC_ENET */
+#endif /* CONFIG_RESV_RAM */
 
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE