sun6i: Poke magic sram controller register to avoid cache issues

Without this the cache will only work in write-through mode, and as soon as
it is put in write-back mode things break.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6c812fc6e9ce351c4dddf910a978c5c3ffe442d9..9b3e80c24aa60c81840dca63e3d7deca2594d9c7 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -114,6 +114,11 @@ void reset_cpu(ulong addr)
 /* do some early init */
 void s_init(void)
 {
+#if defined CONFIG_SPL_BUILD && defined CONFIG_MACH_SUN6I
+       /* Magic (undocmented) value taken from boot0, without this DRAM
+        * access gets messed up (seems cache related) */
+       setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#endif
 #if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
                defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
        /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */