riscv: dts: jh7110: Add clock source from PLL

Change the PLL clock source from syscrg to sys_syscon child node.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index 710b082766d72ed7973368982a56da95063a62d2..b90e7f899544868cf848ede65f1af9ceb58d1177 100644 (file)
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -313,9 +313,9 @@
                          <&syscrg JH7110_SYSCLK_BUS_ROOT>,
                          <&syscrg JH7110_SYSCLK_PERH_ROOT>,
                          <&syscrg JH7110_SYSCLK_QSPI_REF>;
-       assigned-clock-parents = <&syscrg JH7110_SYSCLK_PLL0_OUT>,
-                                <&syscrg JH7110_SYSCLK_PLL2_OUT>,
-                                <&syscrg JH7110_SYSCLK_PLL2_OUT>,
+       assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>,
+                                <&pllclk JH7110_SYSCLK_PLL2_OUT>,
+                                <&pllclk JH7110_SYSCLK_PLL2_OUT>,
                                 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
        assigned-clock-rates = <0>, <0>, <0>, <0>;
 };

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index c22119518c8025a7974bc34590f877df9d84e353..2f560e7296f60e12c9628e01e4343c2743a4e0a1 100644 (file)
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -83,7 +83,6 @@
 
 &syscrg {
        bootph-pre-ram;
-       starfive,sys-syscon = <&sys_syscon>;
 };
 
 &stgcrg {

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 7a8141a8e9f0ce032f8631feeb64f86c1b3f52cc..825fbb7198feb67cfd3e9d7ed146d54d16f88376 100644 (file)
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -487,12 +487,16 @@
                                 <&gmac1_rgmii_rxin>,
                                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
                                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
-                                <&tdm_ext>, <&mclk_ext>;
+                                <&tdm_ext>, <&mclk_ext>,
+                                <&pllclk JH7110_SYSCLK_PLL0_OUT>,
+                                <&pllclk JH7110_SYSCLK_PLL1_OUT>,
+                                <&pllclk JH7110_SYSCLK_PLL2_OUT>;
                        clock-names = "osc", "gmac1_rmii_refin",
                                      "gmac1_rgmii_rxin",
                                      "i2stx_bclk_ext", "i2stx_lrck_ext",
                                      "i2srx_bclk_ext", "i2srx_lrck_ext",
-                                     "tdm_ext", "mclk_ext";
+                                     "tdm_ext", "mclk_ext",
+                                     "pll0_out", "pll1_out", "pll2_out";
                        #clock-cells = <1>;
                        #reset-cells = <1>;
                };