armv7/fsl-ls102xa: Workaround for DDR erratum A008514

This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value: 63b2_0042h comes from the hardware team.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 97ba6d5179ff1d6c90164452917f4e24b8e82701..79ae883b13b7ba88c92e17660ad038b49a7204af 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -76,5 +76,15 @@ int arch_soc_init(void)
                                SCFG_SNPCNFGCR_DBG_RD_WR |
                                SCFG_SNPCNFGCR_EDMA_SNP);
 
+       /*
+        * Memory controller require a register write before being enabled.
+        * Affects: DDR
+        * Register: EDDRTQCFG
+        * Description: Memory controller performance is not optimal with
+        *              default internal target queue register values.
+        * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
+        */
+       out_be32(&scfg->eddrtqcfg, 0x63b20042);
+
        return 0;
 }

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 931727275c1bef090e89b53a4aba95ca64caf592..89339fe0efdc948fcca4773391b4612bda6f2667 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -230,7 +230,7 @@ struct ccsr_scfg {
        u32 scfgrevcr;
        u32 coresrencr;
        u32 pex2pmrdsr;
-       u32 ddrc1cr;
+       u32 eddrtqcfg;
        u32 ddrc2cr;
        u32 ddrc3cr;
        u32 ddrc4cr;