]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
rockchip: rk3399: add tpl support
authorKever Yang <kever.yang@rock-chips.com>
Fri, 9 Nov 2018 03:18:15 +0000 (11:18 +0800)
committerKever Yang <kever.yang@rock-chips.com>
Wed, 8 May 2019 09:34:12 +0000 (17:34 +0800)
Rockchip platform suppose to use TPL(run in SRAM) as dram init and
SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be
limited by SRAM size.
This patch add rk3399-board-tpl.c and its common configs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
arch/arm/mach-rockchip/Kconfig
arch/arm/mach-rockchip/Makefile
arch/arm/mach-rockchip/rk3399-board-tpl.c [new file with mode: 0644]
include/configs/rk3399_common.h

index 48e364e127c39f6a3eee0bc1b7aa4b78d1ecd86d..f5c3329750602568124a323613704b493f543da3 100644 (file)
@@ -154,12 +154,28 @@ config ROCKCHIP_RK3399
        bool "Support Rockchip RK3399"
        select ARM64
        select SUPPORT_SPL
+       select SUPPORT_TPL
        select SPL
+       select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
+       select TPL_NEEDS_SEPARATE_STACK if TPL
        select SPL_SEPARATE_BSS
        select SPL_SERIAL_SUPPORT
        select SPL_DRIVERS_MISC_SUPPORT
        select BOARD_LATE_INIT
        select ROCKCHIP_BROM_HELPER
+       imply TPL_SERIAL_SUPPORT
+       imply TPL_LIBCOMMON_SUPPORT
+       imply TPL_LIBGENERIC_SUPPORT
+       imply TPL_SYS_MALLOC_SIMPLE
+       imply TPL_BOOTROM_SUPPORT
+       imply TPL_DRIVERS_MISC_SUPPORT
+       imply TPL_OF_CONTROL
+       imply TPL_DM
+       imply TPL_REGMAP
+       imply TPL_SYSCON
+       imply TPL_RAM
+       imply TPL_CLK
+       imply TPL_TINY_MEMSET
        help
          The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
          and quad-core Cortex-A53.
@@ -168,6 +184,22 @@ config ROCKCHIP_RK3399
          and video codec support. Peripherals include Gigabit Ethernet,
          USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
 
+if ROCKCHIP_RK3399
+
+config TPL_LDSCRIPT
+       default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
+
+config TPL_TEXT_BASE
+        default 0xff8c2000
+
+config TPL_MAX_SIZE
+        default 188416
+
+config TPL_STACK
+        default 0xff8effff
+
+endif
+
 config ROCKCHIP_RV1108
        bool "Support Rockchip RV1108"
        select CPU_V7A
@@ -195,7 +227,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM
 
 config TPL_ROCKCHIP_BACK_TO_BROM
        bool "TPL returns to bootrom"
-       default y if ROCKCHIP_RK3368
+       default y
        select ROCKCHIP_BROM_HELPER
        depends on TPL
        help
index fd62a693fe6ef742c6bac12a8b0a71d4588976b2..846c82d70a9d6017bb59e349a838aa4a6e75d173 100644 (file)
@@ -12,6 +12,7 @@ obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
 obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o
 obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
 obj-tpl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-tpl.o
+obj-tpl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-tpl.o
 
 obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
 obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c
new file mode 100644 (file)
index 0000000..86d3ffe
--- /dev/null
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+
+#define TIMER_CHN10_BASE       0xff8680a0
+#define TIMER_END_COUNT_L      0x00
+#define TIMER_END_COUNT_H      0x04
+#define TIMER_INIT_COUNT_L     0x10
+#define TIMER_INIT_COUNT_H     0x14
+#define TIMER_CONTROL_REG      0x1c
+
+#define TIMER_EN       0x1
+#define        TIMER_FMODE     (0 << 1)
+#define        TIMER_RMODE     (1 << 1)
+
+void secure_timer_init(void)
+{
+       writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
+       writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
+       writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
+       writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
+       writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
+}
+
+void board_init_f(ulong dummy)
+{
+       struct udevice *dev;
+       int ret;
+
+#ifdef CONFIG_DEBUG_UART
+       debug_uart_init();
+       /*
+        * Debug UART can be used from here if required:
+        *
+        * debug_uart_init();
+        * printch('a');
+        * printhex8(0x1234);
+        * printascii("string");
+        */
+       printascii("U-Boot TPL board init\n");
+#endif
+       ret = spl_early_init();
+       if (ret) {
+               debug("spl_early_init() failed: %d\n", ret);
+               hang();
+       }
+
+       secure_timer_init();
+
+       ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+       if (ret) {
+               pr_err("DRAM init failed: %d\n", ret);
+               return;
+       }
+}
+
+void board_return_to_bootrom(void)
+{
+       back_to_bootrom(BROM_BOOT_NEXTSTAGE);
+}
+
+u32 spl_boot_device(void)
+{
+       return BOOT_DEVICE_BOOTROM;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+       /* Just empty function now - can't decide what to choose */
+       debug("%s: %s\n", __func__, name);
+
+       return 0;
+}
+#endif
index e7ae2c4640d0a1e4e668d93276092d8f45aa33e7..f31f2658bb81175abc9a0732d7426d705e961aa0 100644 (file)
 
 #define CONFIG_SYS_INIT_SP_ADDR                0x00300000
 #define CONFIG_SYS_LOAD_ADDR           0x00800800
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT)
+#define CONFIG_SPL_STACK               0x00400000
+#define CONFIG_SPL_MAX_SIZE             0x100000
+#define CONFIG_SPL_BSS_START_ADDR      0x00400000
+#define CONFIG_SPL_BSS_MAX_SIZE         0x2000
+#else
 #define CONFIG_SPL_STACK               0xff8effff
 #define CONFIG_SPL_MAX_SIZE            0x30000 - 0x2000
 /*  BSS setup */
 #define CONFIG_SPL_BSS_START_ADDR       0xff8e0000
 #define CONFIG_SPL_BSS_MAX_SIZE         0x10000
+#endif
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* 64M */