x86: broadwell: Move init of debug UART to cpu.c

At present the debug UART is set up in sdram.c which is not the best place
since it has nothing in particular to do with SDRAM. Since we want to
support initing this in SPL too, move it to a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: added 'broadwell' tag in the commit title]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
index 232fa40eb53e54d0548cc3ff60c00d5fd2cd59a4..d53c7b863fbf91cbafd3a4be5b3177fe2ef203a0 100644 (file)
--- a/arch/x86/cpu/broadwell/cpu.c
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -12,7 +12,9 @@
 #include <asm/cpu_x86.h>
 #include <asm/cpu_common.h>
 #include <asm/intel_regs.h>
+#include <asm/lpc_common.h>
 #include <asm/msr.h>
+#include <asm/pci.h>
 #include <asm/post.h>
 #include <asm/turbo.h>
 #include <asm/arch/cpu.h>
@@ -156,6 +158,17 @@ int print_cpuinfo(void)
        return 0;
 }
 
+void board_debug_uart_init(void)
+{
+       struct udevice *bus = NULL;
+
+       /* com1 / com2 decode range */
+       pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
+
+       pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN,
+                            PCI_SIZE_16);
+}
+
 /*
  * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
  * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly

diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index b8450cc9d29301885d8407efaa25d1699b28df4c..b31d78c092ada20ac94902fa3b2c34ffc8c45776 100644 (file)
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -194,17 +194,6 @@ int misc_init_r(void)
        return 0;
 }
 
-void board_debug_uart_init(void)
-{
-       struct udevice *bus = NULL;
-
-       /* com1 / com2 decode range */
-       pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
-
-       pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN,
-                            PCI_SIZE_16);
-}
-
 static const struct udevice_id broadwell_syscon_ids[] = {
        { .compatible = "intel,me", .data = X86_SYSCON_ME },
        { }