net: jr2: Reset switch

Make sure to reset the switch core at probe time.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>

diff --git a/arch/mips/dts/mscc,jr2.dtsi b/arch/mips/dts/mscc,jr2.dtsi
index c44e9a2b3ab0c8e5e524882315efc72be8d0f18a..87db7cae9c16a7d380f0bcaf2deb91a17a947305 100644 (file)
--- a/arch/mips/dts/mscc,jr2.dtsi
+++ b/arch/mips/dts/mscc,jr2.dtsi
@@ -243,7 +243,9 @@
                              <0x017d0000 0x10000>,  // QFWD
                              <0x01020000 0x20000>,  // QS
                              <0x017e0000 0x10000>,  // QSYS
-                             <0x01b00000 0x80000>;  // REW
+                             <0x01b00000 0x80000>,  // REW
+                             <0x01010000 0x100>,    // GCB
+                             <0x00000000 0x100>;    // ICPU
                        reg-names = "port0", "port1", "port2", "port3", "port4",
                                    "port5", "port6", "port7", "port8", "port9",
                                    "port10", "port11", "port12", "port13",
@@ -257,7 +259,7 @@
                                    "port42", "port43", "port44", "port45",
                                    "port46", "port47", "ana_ac", "ana_cl",
                                    "ana_l2", "asm", "hsio", "lrn", "qfwd",
-                                   "qs", "qsys", "rew";
+                                   "qs", "qsys", "rew", "gcb", "icpu";
                        status = "okay";
 
                        ethernet-ports {

diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c
index 128d7f21ce0283285c48b2437f09b23fbe64ac81..9ba6ccc1bba27648f2e783d365e507d7a4548fe6 100644 (file)
--- a/drivers/net/mscc_eswitch/jr2_switch.c
+++ b/drivers/net/mscc_eswitch/jr2_switch.c
@@ -235,7 +235,7 @@ static const char * const regs_names[] = {
        "port36", "port37", "port38", "port39", "port40", "port41", "port42",
        "port43", "port44", "port45", "port46", "port47",
        "ana_ac", "ana_cl", "ana_l2", "asm", "hsio", "lrn",
-       "qfwd", "qs", "qsys", "rew",
+       "qfwd", "qs", "qsys", "rew", "gcb", "icpu",
 };
 
 #define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
@@ -252,6 +252,8 @@ enum jr2_ctrl_regs {
        QS,
        QSYS,
        REW,
+       GCB,
+       ICPU,
 };
 
 #define JR2_MIIM_BUS_COUNT 3
@@ -850,6 +852,7 @@ static int jr2_probe(struct udevice *dev)
        struct mii_dev *bus;
        struct ofnode_phandle_args phandle;
        struct phy_device *phy;
+       u32 val;
 
        if (!priv)
                return -EINVAL;
@@ -865,6 +868,17 @@ static int jr2_probe(struct udevice *dev)
                }
        }
 
+       val = readl(priv->regs[ICPU] + ICPU_RESET);
+       val |= ICPU_RESET_CORE_RST_PROTECT;
+       writel(val, priv->regs[ICPU] + ICPU_RESET);
+
+       val = readl(priv->regs[GCB] + PERF_SOFT_RST);
+       val |= PERF_SOFT_RST_SOFT_SWC_RST;
+       writel(val, priv->regs[GCB] + PERF_SOFT_RST);
+
+       while (readl(priv->regs[GCB] + PERF_SOFT_RST) & PERF_SOFT_RST_SOFT_SWC_RST)
+               ;
+
        /* Initialize miim buses */
        memset(&miim, 0x0, sizeof(struct mscc_miim_dev) * JR2_MIIM_BUS_COUNT);