85xx: Add defines for BUCSR bits to make code more readable

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index dab784efa4553172c4787ed04c9bbbe5a25a3c1d..69fce927a6c8d81c12591add6e24f8898dc079e1 100644 (file)
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
  * Kumar Gala <kumar.gala@freescale.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -61,7 +61,8 @@ __secondary_start_page:
 #endif
 
        /* Enable branch prediction */
-       li      r3,0x201
+       lis     r3,BUCSR_ENABLE@h
+       ori     r3,r3,BUCSR_ENABLE@l
        mtspr   SPRN_BUCSR,r3
 
        /* Ensure TB is 0 */

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index af18c1c8ed6a8a8515275251153f1a182c78b429..52ea9b3416761916bd3bdd2a9d20e19e8f0f76e4 100644 (file)
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
  * Copyright (C) 2003  Motorola,Inc.
  *
  * See file CREDITS for list of people who contributed to this
@@ -213,8 +213,9 @@ _start_e500:
 
        /* Enable Branch Prediction */
 #if defined(CONFIG_BTB)
-       li      r0,0x201                /* BBFI = 1, BPEN = 1 */
-       mtspr   BUCSR,r0
+       lis     r0,BUCSR_ENABLE@h
+       ori     r0,r0,BUCSR_ENABLE@l
+       mtspr   SPRN_BUCSR,r0
 #endif
 
 #if defined(CONFIG_SYS_INIT_DBCR)

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 9b3d616a6713fe3ed07cc3810aae75d4b1d5c303..4134f189a44391a1a37661a016308a88224dec49 100644 (file)
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -533,6 +533,9 @@
 #define SPRN_MCSRR0    0x23a   /* Machine Check Save and Restore Register 0 */
 #define SPRN_MCSRR1    0x23b   /* Machine Check Save and Restore Register 1 */
 #define SPRN_BUCSR     0x3f5   /* Branch Control and Status Register */
+#define          BUCSR_BBFI    0x00000200      /* Branch buffer flash invalidate */
+#define          BUCSR_BPEN    0x00000001      /* Branch prediction enable */
+#define   BUCSR_ENABLE (BUCSR_BBFI|BUCSR_BPEN)
 #define SPRN_BBEAR     0x201   /* Branch Buffer Entry Address Register */
 #define SPRN_BBTAR     0x202   /* Branch Buffer Target Address Register */
 #define SPRN_PID1      0x279   /* Process ID Register 1 */