arm: mvebu: Make ECC support configurable on Armada XP

Currently, ECC support is enabled for all Armada XP boards. So the
DDR3 driver tries to configure the controller with ECC support, even
on boards without ECC. This patch makes this ECC optional which now
can be configured on a board-per-board basis.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Phil Sutter <phil@nwl.cc>

diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h
index d9e33f7c6e25602726d7c8fa077439037862d511..75d315a35e0c28cf91b84cb0a6641bad1eab5514 100644 (file)
--- a/drivers/ddr/marvell/axp/ddr3_axp.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp.h
@@ -33,7 +33,10 @@
 #define SAR1_CPU_CORE_MASK             0x00000018
 #define SAR1_CPU_CORE_OFFSET           3
 
+/* Only enable ECC if the board selects it */
+#ifdef CONFIG_BOARD_ECC_SUPPORT
 #define ECC_SUPPORT
+#endif
 #define NEW_FABRIC_TWSI_ADDR           0x4E
 #ifdef CONFIG_DB_784MP_GP
 #define BUS_WIDTH_ECC_TWSI_ADDR                0x4E

diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h
index a6720442ffae5d06c7f9ddd3d4fa8b4e01b5b010..25c34fb01151b9c5c588e597d5e4f909b58ff14e 100644 (file)
--- a/drivers/ddr/marvell/axp/ddr3_axp_config.h
+++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h
@@ -44,7 +44,12 @@
  * DDR3_TRAINING_DEBUG - Debug prints of internal code
  */
 #define DDR_TARGET_FABRIC                      5
+/* Only enable ECC if the board selects it */
+#ifdef CONFIG_BOARD_ECC_SUPPORT
 #define DRAM_ECC                               1
+#else
+#define DRAM_ECC                               0
+#endif
 
 #ifdef MV_DDR_32BIT
 #define BUS_WIDTH                               32

diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index e988f020ab60f3f76d365fab93c58b60c0f2e4f8..c354e6f0d82389d7db4f4c6f4e56b733a2b59083 100644 (file)
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -146,5 +146,6 @@
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 #define CONFIG_SYS_MVEBU_DDR_AXP
 #define CONFIG_SPD_EEPROM              0x4e
+#define CONFIG_BOARD_ECC_SUPPORT       /* this board supports ECC */
 
 #endif /* _CONFIG_DB_MV7846MP_GP_H */

diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 49e83c0fc63c61606689f1514317388ae4cdf0b6..23e552646dca81796f6ec83f6183db3343b7ff16 100644 (file)
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -108,5 +108,6 @@
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 #define CONFIG_SYS_MVEBU_DDR_AXP
 #define CONFIG_DDR_FIXED_SIZE          (1 << 20)       /* 1GiB */
+#define CONFIG_BOARD_ECC_SUPPORT       /* this board supports ECC */
 
 #endif /* _CONFIG_DB_MV7846MP_GP_H */