mx6cuboxi: Fix Ethernet after DT sync with Linux

The i.MX6 Cubox-i and HummingBoards can have different PHYs at varying
addresses. U-Boot needs to auto-detect which phy is actually present,
and at which address it is responding.

Auto-detection from multiple phy nodes specified in device-tree does not
currently work correct. As a work-around merge all three possible phys
into one node with the special address 0xffffffff which indicates to the
generic phy driver to probe all addresses.

Signed-off-by: Josua Mayer <josua@solid-run.com>
[fabio: Added the changes to imx6qdl-sr-som-u-boot.dtsi.]
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Christian Gmeiner <cgmeiner@igalia.com>
Tested-by: Christian Gmeiner <cgmeiner@igalia.com>

diff --git a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi
index e9b188ed65872803f0d94520b26c592b50109750..358cf8abc4ff3679b6b7a9a20862c4002d0e8bcf 100644 (file)
--- a/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-hummingboard2-emmc-som-v15-u-boot.dtsi
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 
 #include "imx6qdl-u-boot.dtsi"
+#include "imx6qdl-sr-som-u-boot.dtsi"
 
 / {
        board-detect {

diff --git a/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi b/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi
new file mode 100644 (file)
index 0000000..0bd7df0
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-sr-som-u-boot.dtsi
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include <dt-bindings/gpio/gpio.h>
+
+&fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
+       phy-handle = <&phy>;
+       phy-mode = "rgmii-id";
+
+       /*
+        * The PHY seems to require a long-enough reset duration to avoid
+        * some rare issues where the PHY gets stuck in an inconsistent and
+        * non-functional state at boot-up. 10ms proved to be fine .
+        */
+       phy-reset-duration = <10>;
+       phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
+       status = "okay";
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethernet-phy@0 {
+                       status = "disabled";
+               };
+
+               ethernet-phy@1 {
+                       status = "disabled";
+               };
+
+               ethernet-phy@4 {
+                       status = "disabled";
+               };
+
+               phy: ethernet-phy@ffffffff {
+                       /*
+                        * The PHY can appear either:
+                        * - AR8035: at address 0 or 4
+                        * - ADIN1300: at address 1
+                        * Actual address being detected at runtime.
+                        */
+                       reg = <0xffffffff>;
+                       qca,clk-out-frequency = <125000000>;
+                       qca,smarteee-tw-us-1g = <24>;
+                       adi,phy-output-clock = "125mhz-free-running";
+               };
+       };
+};